I am a newbie to Labview and FPGA programming... I am using NI PXIe-8133 Controller card and NI-5781 FlexRio card. My task is to take input of 20 MHz external signal and then process it further... I have to transfer that signal from FPGA to RT with the use of FIFO (that is what I understand). I referred the following example and succeeded in transferring a low frequency signal (range of KHz) from FPGA to RT as the sampling rate is in micro seconds.
But I want to have sampling rate in nanoseconds if I want to take a signal of 20 MHz. How can I achieve that? Is there any alternate method apart from FIFO to achieve that task?
I am a starter in Labview, your help will be appreciated...
Please ensure that you have all support for FlexRIO installed and then look into the following example (path might be slightly different dependent if you are using 32-bit OS or 64-bit OS and LabVIEW version).
C:\Program Files (x86)\National Instruments\LabVIEW 2012\examples\FlexRIO\IO Modules\NI 5781\NI 5781 Getting Started
That project is a good starting point for you to set up the acquisition properly (upper two loops, might not need the generation loop, not sure what you want to do more).
The middle loop (Analog Input) handles the DMA transfer to host application and depending if you need generation you can modify the corresponding host code as well (remove analog output related code). Then look into “Producer/Consumer design patterns (data)” where one make use of queues to send data from one loop (your analog input related loop in your RT host code) to an additional loop where you do your file I/O. Look for TDMS or binary file I/O examples.
Thank you very much for your help. The example really helped me to understand the input/out operation.
My application is to take a 20 MHz 'Phase Modulated' signal to FPGA and demodulate it. As a first step i want to take any arbitary signal of Mhz range and examine it if i am getting any phase noise or any other change in attributes.
I tried to give input signal to FPGA transferred it to RT and plotted it. Also from RT i sent the signal again on FPGA out pin to check on Oscilloscope and compare with the given input signal. Now my problem is I can see the signal on the RT signal plotter but I am not getting any signal back on FPGA pin. I have used Two different FIFOs for Target to Host and Host to Target communication.
It will be helpfull for me if you comment on my designed program for the said purpose. Here I have attached the screenshot of RT front panel. Also attached my FPGA and HOST vi files.
You're trying to write to the output at 40MHz. You won't be able to generate a signal at that rate on the RT and to transfer the signal from the RT to the FPGA at that rate. What signal do you output? Can't you generate the signal on the FPGA and only send the signal properties (amplitude, frequency, ...) from the RT?
Or do you want to keep the output value until you get a new element? Then you will have to store valid values in a shift register and use the stored value when the FIFO_OUT times out.
EDIT: sorry, didn't look at the Host code before. If you just want to output the input signal why don't you do that directly on the FPGA?
You can change your code in a few ways and here is the simplest one.
Change your Host code so you configure the FIFOs (method just as the “Start” one you are using now) and then start them (sequentially) i.e. FIFO_In and then FIFO_Out where you control execution flow with the FPGA ref wire and error cluster (not splitting as you do now).
One thing confuses me a little bit – why do you acquire data, send it through DMA to host and then back to FPGA again and then out on an AO pin? If you would do it on the processed data it would make more sense. If you just want to send it out on AO again (without any processing taking place on the acquired data) why not just send it to local (target scoped) FIFO on the FPGA in the acquisition loop and then in another loop on the FPGA read the FIFO and output it on AO pin?
If you have a SSP agreement to the LabVIEW license you have the possibility to call your local NI support.
Hi dan_u and Jimmie_A
Thank you for your replies.... I like to mention here that in my application i have to take a 20 MHz, Phase modulated signal input at FPGA and then demodulate it. So it is very important that the phase information should be intact when i am taking signal in to the FPGA using FIFO. Now why i was trying to take singnal on RT and back to FPGA is because I was planning to demodulate signal on RT, but before going to demodulation programming I have to first be sure that the given input signal is having all phase, frequency and amplitude values intact. So I want the signal again out so at primary stage i can compare my FPGA accepted signal with my original signal.
Now as u suggested Jimmie_A, I have already tried the target-to-target FIFO to take signal out directly from FPGA without transferring to RT. In this experiment i could get output signal but the signal is not retaining the properties of given input signal on FPGA pin. Frequency information is fine but amplitude is being attenuated. If i give 2V signal to the input pin, at the output pin i get only about 500mV signal. I am also not able to detect any phase change at output as i am changing phase of input.
I have attached the screenshot of my vi. kindly comment on the issue...
Thanks a lot....
FIFOs are primary used for transferring data from one loop to another and you are currently pushing data into the FIFO and then directly read from the very same FIFO i.e. it is the same thing as wiring AI directly to AO.
I would read through the getting started document for the 5781 that clearly go through various examples including a loop back example where data is being generated on AO and read on AI. Look at that example, modify as needed since you basically want do to the reverse.
It gets interesting for your part from page 10 and onwards.