To run a HDL code on FPGA??

[sathya123]

Hi all,

            My project holds two VI. One with the target device and other on the HOST side.

Host.vi - Comprises of File Operations and a bit file uploaded.

Target.vi - Performs the HDL node execution.(.bit generated)

Issue: HDL code runs at 40MHz and Host runs at the system clock(I suppose). So, the output file comprises of data repeatedly.

How do i synchronize both? Or is there any chance of accomplishing this issue without synchronizing(Ex. any handshaking kind)??

[andre.buurman@carya]

Have a look at the different cRIO resources available that explain how to create a cRIO application.