Timing error in my fpga code

[kprabaka]

Hello everyone, I have attached a image with this which basically indicates an error that I am getting when I compile my FPGA code. I have also attached a picture of my code with this. I am a newbie in Labview FPGA and this code might not be  the efficient way to acheive what I am trying accomplish. Basically the following is the application. 

I have an sbrio 9642 and I am getting six analog inputs and I would like to get the RMS value of these six analog signals as accurate as possible. The inputs are pure sinusoids with a frequency of 60 HZ. 

If anyone have any questions about the code or the application, please post in this discussion. I will try to answer as fast as possible. 

Regards,

Kumar

[crossrulz]

I'm not immediately seeing anything out of the ordinary.  But you could remove the large Compound Arithmetic Node.  Since all of the RMS values should become lid at the same time, just wire only one of the boolean outputs to the case selector.  That should save some gates (that is a bunch of ANDs) and just maybe speed up the processing enough to get that timing in spec.

[Dragis]

What rate is your default top-level clock?

[kprabaka]

Hi, I tried removing the compound arithmetic node but it did not work. I think whenever I use more than one RMS block, I get such error. 

[kprabaka]

I am using a sbrio 9642. I think in this device it is 40 Mhz.

[Dragis]

Can you try getting rid of the one big case structure and put one around each indicator using the output valid from the single upstream node to control when each indicator gets written. Just trying to remove any "external" affects from each data path to see where things break down.

[kprabaka]

Hi, I have changed my code as you have mentioned (picture below). But, I still receive the error. 

I think it has something to do with the FPGA clock speed. I tried changing the clock speed from 40 to 80 MHZ and 120 MHZ. It did not help. 

.

[dan_u]

The timing error says "Requirement 12.49ns". So obviously the compiler tries to compile for 80MHz.

How did you change the clock speed? Are you sure you're using the 40MHz clock as Top-Level Clock?

[Dragis]

Yeah, I read your first error image as 25 ns but it is actually 12.5 ns which is an 80 MHz clock. Make sure your top-level clock is set at 40 MHz or lower. In the project tree you'll have one clock marked as the default, that's what we're talking about.

[T-REX$]

Hey dan_u,

Actually, the 80MHz is correct... It's failing on the communication to the "module" that's onboard. This interface is supposed to run at 80MHz, even with a 40MHz top-level clock.

@Kumar,

Can you post the Xilinx log, and maybe a screenshot of the resource utilization? Also, a screenshot as above, with the last item selected would be useful (the one with the 5.2ns routing delay)