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Timing Violation FPGA

I´ve got a problem using an fpga with the code in a while loop. Sometimes the compilation worked, but now, as I optimized the code I do always get a "timing violation" when compiling. I reduced the code as much as possible, but the error ocurred again. By the way sometimes the compilation worked when using a code even more complex than the present version.

 

I attached the fpga.vi. When necessary I can also upload my rt.vi communicating with the fpga.

 

Thanks for solutions,

Tom

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Can you provide the specific error that you're seeing?

 

As I understand it, an FPGA timing violation means you're asking the FPGA to do more in a single clock cycle than it is capable of doing.  This is not necessarily related to the complexity of your code, since the FPGA can do multiple tasks in parallel.  It is an issue of how many interdependent instructions happen in series.  If you can determine where the error is occurring, you may be able to solve it by inserting a feedback node.  This breaks up one continuous chain of operations into two cycles, but delays processing of the data by one loop cycle.

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I can post the exact error tomorrow, but it´s not specified by a certain error code. The message is: "The compilation failed" (in the compilation window) and "Watch timing violation analysis". By the way: last week I could compile the identical vi.

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attached below is the displayed error

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In the future, please attach images directly rather than embedding them in an Excel document.  PNG is the preferred format (you can paste into "mspaint" as easily as into Excel) but GIF and JPG are acceptable too.

 

Have you changed your synthesis optimization goal since the previous working compile?  That's the only thing I can think of.  Perhaps someone from NI will have a suggestion next week (today is a holiday in the US).

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The synthesis optimization goal is optimized to speed, so it is still the right thing, as we have a timing problem.

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