Timed loop jitter during communication between real time target and FPGA

[omkara2233]

Hello Everyone,

I am running timed loop on RT target which sends torque FXP values to FPGA using FPGA read write block.

But I see spikes in cycle time from 100 to 7000 micro seconds as shown below.

 

I narrowed down root of problem by sending only one shared variable when cycle time is deterministic vs. sending 6 shared variables when I see these spikes. I am guessing as number of variables increasing so the wait time which results into these spikes. How can I solve this issue, do I need array to send data from all variables at ones or something else. Any help or direction is much appreciated.

[GerdW]

Hi omkara,

don't use SharedVariables in time critical loops!

I recommend to take the "RealTime2" self-paced course as currently offered for free from NI!

[omkara2233]

Hi GerdW,

Shared variables in vi are RT FIFO's as per real time2 course.

In my second try I got rid off shared variable to find root of problem and directly connected torque variables to fpga read write block as shown below. But thinks didn't change and got same cycle spikes. Which made me think the issue is between RT target and FPGA.

[crossrulz]

1. Network activity is non-deterministic.

2. Network Published Shared Variables (NPSVs) are pure evil.  They introduce all kinds of weird race conditions, security issues, and anybody on the network can change them on you.

So with that, my recommendation is to use TCP/IP or Network Streams to pass data between host computers and your cRIO.  That should be done in a separate loop.  You can have your deterministic loop read the values using Global Variables or an RT-FIFO.