From Friday, April 19th (11:00 PM CDT) through Saturday, April 20th (2:00 PM CDT), 2024, ni.com will undergo system upgrades that may result in temporary service interruption.
We appreciate your patience as we improve our online experience.
From Friday, April 19th (11:00 PM CDT) through Saturday, April 20th (2:00 PM CDT), 2024, ni.com will undergo system upgrades that may result in temporary service interruption.
We appreciate your patience as we improve our online experience.
01-11-2007 12:23 AM
01-11-2007 02:01 PM
Hi,
I have seen similar issues when waiting for a prox signal or something similar on the FPGA ==> the input would trigger repeatedly during the rising edge and the falling edge of the pulse generated by a prox signal.
To get around this, I introduced some debouncing logic and that resolved my problem. See the figure # 17 in this document: http://zone.ni.com/devzone/cda/tut/p/id/2993 . This is similar to what I did but there are also a few other approaches. If this doesn't work for you, let me know.
Good Luck!
Mike R.
01-17-2007 12:38 AM