Strange LabView/cRIO Digital I/O Behavior

[JustinZZJ]

Hi everyone,

I just got a question about cRIO and LabView.

I am using cRIO-9082 FPGA controller and NI 9401 for sending IGBT gating signals to my power circuitry. I have two separate control programs under the same LabView FPGA project that I am testing. In each program, I have made a Boolean button in LabView that I need to click to start execution my control strategy (or else all gating pulses from NI 9401 are FALSE).

A few days ago, I first ran one of the control programs and everything went well as usual. Then I stopped and closed the program, with all gating signals back to FALSE. Normally, I would first power down my power circuitry, switch to the other program, and then power everything back up again (in retrospect, I don't know why I always did this). But this time, I forgot to do so and kept the circuit powered up, and then once I opened the second program and clicked run button of the LabView (NOT the Boolean button to start executing my code that I have made), somehow the cRIO sent some gating pulses that I didn't issue and caused my IGBT & MOV to be destroyed. This was very unfortunate event, and I just want to ask whether cRIO somehow will generate some random digital outputs when switching and loading another program, or something like that? I felt that this was a strange behavior of cRIO that I did not know before.

Thank you very much and I look forward to your reply.

[rolfk · Accepted solution]

When loading an FPGA program the entire FPGA fabric is of course initialized. This causes the digital IO to go into default state which is normally as an input (that way it will never try to drive into an external signal that may be connected to a pin and eventually destroy the FPGA output or external circuitry because of short circuiting it). Your external hardware should be fail safe in that sense that it won’t do strange things when not actively driven (an input pin acts as a very high impedance). And there can be a very short moment during initialization were not all IO are at the same time in either a previously determined state, the reset state, and/or the new state your new program sets after being loaded and started.

Basically you should have external circuitry that is automatically in failsafe state when not actively driven low or high at its inputs and with a seperate enable line that is activated after you configured all the other signals properly. If you only control low voltage digital circuitry this is all somewhat less critical as they mostly survive transient logic level short circuits on their pins but with high current devices you have to be very careful.

[JustinZZJ]

Dear Rolf,

Your explanation totally made this situation clear to me, and due to my ignorance about this fact, unfortunate event happened.

I am wondering when I stop and then start the same FPGA program, will the digital IO be re-initialized? In other words, does this initialization process only occur when I switch programs, or whenever I start a program even it is the same program?

Thanks!

[rolfk]

I'm not sure. But I NEVER rely on such things in my hardware designs. They will sooner or later come around and bite you in your "derrier".

ALWAYS create fail safe hardware that you have to explicitly enable with a signal, if anything can get damaged. That applies triple as much if human health can get impacted but should be not ignored even for simple hardware.

Then in your software (either in FPGA and/or RT) design a clear initialization sequence that makes sure all signals are set to a sane start value before you enable the hardware.

[JustinZZJ]

Thank you very much Rolf for your help.