07-01-2019 08:06 AM
Hi all,
I've a problem during the sinewave geneartion on cRIO via FPGA with NI9246 module.
I've used the same LV structure found in LV example folder ( Hardware Input and Output->CompactRIO->Signal generation and Processing->Analog->Sine Wave) and adapted at my porject (based on LVOO and actor framework).
I'm anle to generate a signal with right frequency and amplitude but regarding the shape no!!!...I generate a square wave.
I attach the jpg of real time part and the fpga impementation, due to the complexity of the project i can not upload all files.
The cRIO module works with a FXP (int word lenghts 5 bits and word lenght 16, signed)
Any suggestion?
Thanks
T
Solved! Go to Solution.
07-04-2019 07:08 AM
Hi,
the code snippets you attached are not very helpful, but it would actually be useful if you could attach at least a simplified VI allowing to reproduce the sine wave generation.
Other information that could be relevant:
Regards,
Alessia
07-04-2019 08:35 AM - edited 07-04-2019 08:37 AM
Hello,
apologize for my typing error. The AO is NI 9264. I try to generate a sin with f=40Hz and Amplitude =2V (4 Vpp).
I've added the full project based on the NI example. The Amplitude is not a problem, the target is the frequency (reached) and the shape (sin instead of square).
I work with FPGA clock (40Mhz), maybe the problem is due to FXP AO data type ( Int word lenght : 5 bit and word lenght: 20). The Sine Wave Generator2 ( Express VI) has a I16 Output. Have you a suggestion about skip the problem and adapt the Express VI output for the AO ?
Thanks
07-04-2019 08:44 AM
Hello,
apologize for my typing error. The AO is NI 9264. I try to generate a sin with f=40Hz and Amplitude =2V (4 Vpp).
I've added the full project based on the NI example. The Amplitude is not a problem, the target is the frequency (reached) and the shape (sin instead of square).
I work with FPGA clock (40Mhz), maybe the problem is due to FXP AO data type ( Int word lenght : 5 bit and word lenght: 20). The Sine Wave Generator2 ( Express VI) has a I16 Output. Have you a suggestion about skip the problem and adapt the Express VI output for the AO ?
07-08-2019 01:18 AM
Hi.
I've found my mistake...a bad sampling parameters in fpga area ("Desired loop rate" parameters in my example).
Now, seems work.
Thanks
P
07-08-2019 02:01 AM
Hi P,
thanks for the update. Would you be so kind as to specify how you changed the parameters to make the code work (wrong values --> right values)? This information could offer useful insights to other members of the community who may have a similar problem.
Regards,
Alessia
07-08-2019 02:08 AM
Yes, of course.
In the example posted, on fpga module, there is "Desired loop rate (ticks)" parameters. This parameter set the loop scheduling and is necessary set it at the HW sample rate (in my case cRIO 9264 is 25K).
07-08-2019 03:51 AM
Thank you so much!
Best regards,
Alessia
12-07-2021 08:57 AM
Hi there, I am having the same issue, and with changing the sample rate in the HOST vi, nothing change with the signal.
I have a CRio 9039 with a 9264 Module, i am using LV 2020. I tried you Project(which comes from the examples) and I using a scope on output A0.
I still only get pulses, at the right frequency but no sinus wave at all. Can u maybe explain with pictures what variables you change in the FPGA vi or the Host vi?
Thanks in advance.