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Send data with bit length of 110ns using FPGA on sbRIO-9638

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Hi,

 

Hope you are doing well.

 

I am trying to establish serial communication with a device which transmits data at 20 MBuad (106.7 ns bit length). On scope it shows bit length of ~110ns.

 

Default clock frequency on FPGA in use is 40 Mhz (25ns) and I have tried using a derived clock up to 100Mhz which gives me a cycle time of 110ns on 10 cycles. But, it seems like the DIOs on the sbRIO-9638 cannot transmit data at such higher rates. Output data appears unreliable with moving bits.

 

I am not sure about DIO update rate and missing information. Also, do not know if I am trying to achieve something that is not possible with this hardware. Any suggestion or guidance is much appreciated!!

 

P.S. I would be in a really bad place if it comes down to changing the board.

 

 

Thank you for your time.

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Accepted by topic author XM43

Hi Xonmyth,

 


@XM43 wrote:

Default clock frequency on FPGA in use is 40 Mhz (25ns) and I have tried using a derived clock up to 100Mhz which gives me a cycle time of 110ns on 10 cycles. But, it seems like the DIOs on the sbRIO-9638 cannot transmit data at such higher rates. Output data appears unreliable with moving bits.

 

I am not sure about DIO update rate and missing information.


 Why don't you read the specs?

 

And why don't you work with the default 25ns cycle, which allows for loops at 100ns iteration time?

The DO should be able to run at an update rate of 20MHz (or 10MHz in DAQmx mode).

The counters allow for upto 20MHz output rate.

The DIO on IDC connector allow for 40MHz update rate AFAIK (didn't found any numbers)…

 

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Hi GerdW,

 

Thank you for the response.

 

I did read the specification sheet and at first I used the base clock of 40 Mhz which gave me bit length of 100ns. As I previously mentioned, the device that I am trying to communicate to deals with bit lengths of 110ns. I am not sure if 10ns (6.7ns) of added bit length will make a difference. As overall pulse comes out be to ~40ns shorter for the same data.

 

Since there is no literature available for the device that I am trying to communicate to, I have been simply recreating signals that I captured from scope and logic analyzer. Crossing out this doubt will help me. Even an AFAIK answer would help.

 

Thanks

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