SPI on myRIO with synchronous 8 channel ADC

[USF_ENG]

Hello I am working on an acoustic direction finding project that uses time difference of arrival of 8 analog microphones to determine the direction of an acoustic event. I have an ads1278 which provides delta sigma ADC. I have not done any SPI parsing on LabVIEW so I am trying to get some help on what my limitations are and what the community would recommend for the best implementation for a beginner like myself. I see the default SPI VI can run up to 16 bits, so I am curious would I only be able to run the 24 bit ADC device through FPGA? If I acquired the ADS1178 (same link) 16 bit version that provides a slower sampling rate, could I get the MISO through the default SPI VI and avoid using FPGA? Any help will be greatly appreciated! 

Thanks.

[cbutcher]

Hi USF_ENG,

I'm not sure what 'default SPI VI' you're talking about. Could you provide the VI file or a link? I couldn't see anything in the LV Example Finder, and when I have implemented a DAQmx-based SPI communication in the past, I don't remember anything about 16-bit limitations.

The NI White Paper on SPI communication links to some example implementations. This reference design shows some useful information about using SPI communication with LabVIEW.

I've used the implementation titled something like 'Using an Internal Sample Clock' under the DAQmx device section on the reference design page. It uses the library linked here (although I had to use the low-level subVIs (Add {First,Middle,Last} Bit.vi) rather than the higher level {Send,Swap,Receive}.vi.

Is it these VIs you mean by the 'default SPI VI'? They are polymorphic with 8/16/32/64 bits, but that didn't work out for me (I needed to send stranger length sections, although presumably I could have padded the beginning or end with 0s and sent 64 bit sections in some cases...)

[USF_ENG]

Hello Cbutcher,

Thanks for the quick response. By default VI I was referring to the SPI express VI which comes as part of the myRIO toolkit scene here SPI Express VI and looks like this, 

It gives the option of choosing anywhere from 4 bits to 16 and max of 4MHz (this may be a limitation from the myRIO). I believe I will have to use an approach similar to this, FPGA-SPI. It looks like I should be able to use a 24 bit SPI device through custom FPGA, but I wanted to make sure it was possible, and how I should best go about it since I have never done SPI or FPGA on the myRIO. 

[cbutcher · Accepted solution]

Ah. Then perhaps someone will correct me if I'm wrong, but I don't think that frame length (your 4-16 bit value) has anything to do with the possible accuracy you can read from your ADC. This only describes the amount of data to send in one chunk. Your 'Read' option also allows you to specify a number of frames.

The ADC generates a digital value and has some communication method to send that value, but your frame length is like the amount of data to send at once - a page describing this is linked from the myRIO article you linked and I relink it here: http://dlnware.com/theory/SPI-Frames

When you read your data in for example 8 bit chunks, you just need to be aware that you'll need 3 frames to get the 24 bits that you expect to represent the value you converted. How you put these back together probably depends on the ordering of the bits, but something like this might give you an idea (trial and error will get you the right values, if you can do it that way - looking up the manual is no doubt a better plan)

Given it's not unlikely you want floating point numbers, more effort will probably be needed, but it's likely to just involve reading a few values and stitching them into a subVI that recombines them and gives you a 'double' output, or similar.

[USF_ENG]

Ok great that is relieving to know.Thanks for the help.

[Lily1979]

Hello,

I

I need send a 32 bits to the chip AD5628 with myRIO SPI express VI, but the frame length max is 16 bits. So I need send 2 frames of 16bits, but there is 120µs between these two frames. 

what can I do if I want to use this SPI expresse VI? 

Thanks,

Lily

[alyssa.h]

Dear Lily1979,

You are more likely to get a response if you create a new post for your question. Since this one already has an answer, it isn't likely to be looked at.

[Lily1979]

Thank you.

I did it in FPGA and it works.

Lily

[ArnauSegura]

Hi Lily1979,

May I ask you how you managed toset up the FPGA SPI implementation you need? I'm using NI's IP and it seems to compile but the communication loop itself does not run.

[BdogTheWatchdog]

Hey Arnau,

It looks like Lily mentioned using the SPI Express VI. Check out this short YouTube video that sums that function up pretty well.

Are you running the example linked at the bottom of that page, or implementing the IP? In either case, this forum thread is over a year old and you would be better off creating a new forum post for enhanced visibility.

Bdog