Receive high speed ADC output data with Labview FPGA

[johnsnow34]

Hello,

I'm using sbRIO9651 to receive outputs data of ADC (LTC2174) with Labview FPGA.

I have a question about it:

The data clock output (DCO) of ADC is 400MHz. If I use a SCTL with a 100MHz clock which is derived from DCO, for data acquisition (see the picture), the data outputs will at each iteration export more data bits or just at one iteration export one bit?

[GerdW]

Hi john,

THINK DATAFLOW!

Your loop iterates at 100MHz. In the loop you are reading digital inputs, each one is giving you a single boolean value…

[johnsnow34]

Hi GerdW,

thanks for your reply. You mean each data output exports one boolean value at each iteration?

If so, how can I receive all boolean values of each output without data loss? The DCO(400MHz) is too fast, so I can't directly use it as the iteration clock of SCTL. But except SCTL, I don't know if there are other ways to receive the data at this high speed.

Best regards,

John

[Terry_ALE]

When the clock rate is slower than the rate of the I/Os, LabVIEW FPGA has multiple I/Os e.g. AI0N, AI0N-1, AI0N-2, AI0N-3 (or similar).

By reading these, you get parallel data which allows you to maintain the throughput.  I am not familiar with this card or your config.  Could you post screenshots of the pin outs under the Socket from the project (or post the project)?

[johnsnow34]

Hi Terry,

you mean configure all data outputs as one I/O node with sbRIO CLIP Generator, e.g. UInt8 type (like picture 1)?picture 1

This can truly make each output parallel exporting data. But the data rate of each output is still same as before and is faster than the clock of SCTL. So there will also be data loss.

The physical connection form between ADC outputs and FPGA I/O is: Each ADC output lane (Out1A, Out1B...Out4B) is connected to one DIO of FPGA. When ADC is working, each output lane will export data bit (boolean value) at 400MHz DCO.

Picture 2 is the current pin under Socket from the project. In the attachment it's project files. Could you have a look at them. Thanks.picture 2

Best regards,

John

[Terry_ALE]

Not like picture 1.

I do not use sbRIO but I have worked with other NI FPGA hardware that runs at higher the rate of the SCTL.  Besides the sbRIO-9651 http://www.ni.com/pdf/manuals/376962c.pdf what other hardware are you using?  I am unable to find the reference to the 400 MHz DCO.

[johnsnow34]

Hi Terry_ALE,

sorry for the delayed reply. sbRIO 9651 is the first NI hardware that I used for development work. Now I'm trying to reduce the sampling rate of ADC, then DCO of ADC will also be automatic reduced. In this way, I think Labview can handle it better under a slower rate. Thanks for your help.

Best regards,

John