Real-time PID Controller with NI PXI 8176 Real-time controller, and NI PXI 7831R FPGA Board

[Giray]

I am using Labview 2009 FPGA module to develop a Real-time PID controller. My devices are NI PXI 8176 Real-time controller, and NI PXI 7831R FPGA Board, both on the PXI chassis 1042. The application requires one analog input and one analog output in simultaneous operation. The input signal is acquired in the FPGA VI and then transferred to the Host VI by means of DMA FIFO. After some data processing in the Host VI, the processed data is passed back to the FPGA VI, again by means of DMA FIFO. This data is the data to be controlled by the FPGA PID function. Then the data is passed through the PID function, and sent to one of the analog output channels of the FPGA.

I tested the code described above with some standard generated signals. I can successfully transfer the data to Host, and do the data processing. However, when I connect my analog output to the oscilloscope, it looks like I am not receiving anything from the output. I checked my BNC and physical connections and they work fine. Either I am not able to get the processed data from the Host back to the FPGA, or I am not using the analog output functions of the FPGA right. I do not have much experience with the FPGA module, so I might be doing something fundamentally wrong here. Attached is the host and the fpga VIs.

Thanks for your help,

Giray

[StephanieA]

Giray,

I took a look at your post and have the following idea of what could be happening. Since I only had the VIs and not the project, I wanted to know how you set up your FIFOs. When the FIFO Property Box popped up, did you select one of your FIFOs to be Target to Host - DMA and the other to be Host to Target - DMA? If you are not sure about this, you can right-click on your FIFO and Under the General Category look at the type. 

[Giray]

Stephanie,

Thanks a lot for your quick reply. I checked the FIFOs. One is Target-to-Host, and the other is Host-to-Target. So the directions of the FIFOs seem to be fine. I am also attaching the project itself. Can the problem be about the way I am using the while loops and sequence structures in the FPGA VI? Or, am I possibly making a mistake with the FIFO blocks in the Host VI?

Thanks,

Giray

[StephanieA]

One thing I was curious about your code. If you were to probe the data going into the Peak FIFO on the Host VI, do you receive any data there? If there is no data in the maxArray indicator, then the FPGA would be receiving no data from the FIFO.

I also took a closer look at your code and noticed that you use a lot of individual sequence structures. Using individual sequence structures instead of one with multiple frame does nothing to enforce dataflow. If you are able to click on a frame and move it away from the others, LabVIEW has no way of know which structure to execute first. When using sequence structures, always right-click on the border and select Add Frame.

Have you been able to transfer data from the FPGA and Host successfully before? If this if your first time, I found an example that may be helpful. Simple DMA FIFO Example for FPGA. It may be beneficial to get this example program working and use it as a baseline for your code.

[Giray]

Yes. When I probe the data going into the Peak FIFO on the Host VI, I can observe the processed data there. I also changed my individual sequence structures to multiple frames. I tried the FIFO example and it works fine. But I still could not figure out what is going wrong in the Host VI. Can the problem be about not synchronizing the FPGA clock rates correctly or not synchronizing the FIFOs correctly? Is it faulty that I am trying to use both Target-to-Host and Host-to-Target FIFOs in the same while loop in the FPGA VI?

I also tried placing the data processing part of my code(which currently is in the Host VI) in the FPGA VI. Therefore I only use the Host VI for user interface and inputting variables. FPGA VI now contains both the data processing and the PID functions. But unfortunately I could not get this to work either. I am also attaching this project. Please correct me if I am wrong. Each iteration of the FPGA while loop inlets one data point from the analog input channel. However I need multiple data points in each while loop iteration(at least three) in order to be able to perform the peak detection algorithm which is in the same while loop (second sequence structure). The reason I was transferring the input data to the Host VI before was that I could obtain multiple data points at each while loop iteration. Is there a way to continiously inlet data points to the FPGA VI rather than just obtaining one data point at each while loop iteration?

Although I searched the NI dorums and the Developer Zone quite a bit now, I could not come across an FPGA example where a combination of data acquisition, PID, and data output operations is illustrated. Such an example would be extremely helpful. If there is one and I missed it, could you point me to it if possible?

Thank you very much for your help,

Giray