12-18-2021 10:25 AM
Thanks for your time on this question.
I am trying to transfer data from RT target to FPGA, but I am a little confused about their timing. I have two questions below.
1. How fast can the data be transfered? The goal would be to transfer a double variable at 40 MHz. Can I do that?
2. Is their timing consistent with each other? i.e. RT generates a number per (1 / 40M) sec and FPGA receive it at the next clock? Or is there any way to do that?
Thank you again for your patience. I am really new to embeded system so my questions might sound stupid. Sorry for that if so.
12-18-2021 10:49 AM
1. Throughput rate between RT and FPGA depends on the hardware you are using.
2. RT will generally not be able to handle as much data as an FPGA could generate.
The FPGA could send more than one sample per cycle and the clock rate could vary.
12-18-2021 12:15 PM
You could have the RT generate a bunch of the elements at once in an array and then use a DMA FIFO to pass the data down to the FPGA to do whatever with. Considering you are passing DBLs, I'm not sure what you expect the FPGA to do as any analog outputs will be much slower than the 40MHz you want (I am assuming a cRIO here).
12-18-2021 01:51 PM
If you have hardware that can acquire data at that rate and a signal making it worthwhile, why not flip and acquire in the fpga and process in the slower RT loops?