Reading PWM in FPGA too slow

[MaciejDP]

Hi All,

I have a timed while loop in FPGA (sbRIO 9633) which is returning the Hi and Lo counts in every new PWM cycle (PWM coming from a sensor).  Ticks are coming from a 32 bit Tick counter.  With a 1kHz PWM signal, the Hi and Lo counts are about 9859 each at 50% duty cycle - which is pretty low, and it's severely reducing the effective resolution of my sensor.  How can I increase these numbers?  The timed while loop timing was set to 'top level', then I tried setting it to the 40MHz clock, but it didn't seem to help.

Thanks

Maciej

[KathrynTheGreat]

Hi MaciejDP,

What kind of sample speeds are you aiming to have in this system?

The number of samples you're taking in from the PWM signal works out to about a 20MHz sample rate, much lower than the 40MHz clock the loop is tied to. Did the code compile properly with the timed loop tied to the 40MHz clock, or did it give you a compilation error?

Also, are you working with the program in interactive mode (watching and controlling it from your host PC), or are you allowing it to run headlessly on the RIO? Interactive mode sends quite a bit of information back and forth between the systems, and can cause programs to run much more slowly than expected.