Questions about 64k Hz loop

[TCPIP]

  I am using the LV 8.2 and writing a lot of filters (discrete time filter) in the FPGA VI.

  The unit delay for the discrete filter is expected to be 64k Hz, however, the minimum clock rate that can be derived in SCTL in the FPGA VI is 2.5M Hz, as the filters consume a lot of resources, we cannot use the following method ( a while loop+flats sequence+loop timer while attached the shift registers at the while loop) to implement the filters as using SCTL saves much resources:

  To save the resources used, I put the SCTL inside the while loop. The SCTL still execute at 2.5MHz, but the shift registers are attached at the outside while loop, the while loop will excecute once when the SCTL excecute 39 times, and every 39 times, the SCTL get the same input and produce the same output. The unit delay at the outside while loop was still 64kHz.

Does my implementation consume extra resources

[Van_L]

Hi TCPIP

The purpose of SCTP is to optimize code to execute quickly and consume less space.
It saves space by removing the registers after each combinatorial stage since its forced to execute in 1 clock cycle.
You are definitely saving "some" space here.

You can always compile and refer to the compilation report to see the actual percent you have consume or saved in each scenario.

If you like to optimize more, a very good document on Optimizing FPGA VIs for Speed and Size can be on ni.com or labVIEW help installed on your computer.

Good luck