Question about the latency of high throughput function in LabVIEW FPGA.

[zyb1003]

Hello Everyone, 

Now I use the Arctan2 function to calculate the phase of AI signal, then I want the phase being calculated to be the new phase setpoint of the DDS signal generator in AO loop. The problem is the Arctan2 function itself takes 16 cycles to output a valid data, but my DDS signal generator needs a valid setpoint every cycle. So is there anyway to make from 1-16 cycle, the setpoint use the first valid data, then on the 17th cycle use the second valid data? 

All the codes are within FPGA SCTL. 

Thank you. 

[wiebe@CARYA]

I'd go for a predefined look up table or an approximation. Usually, a full out can be avoided, since there are symmetries, reducing the lut to 1/4 and some logic.

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zyb1003 wrote:

 So is there anyway to make from 1-16 cycle, the setpoint use the first valid data, then on the 17th cycle use the second valid data? 

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You'll have to push the values on a fifo every 16th cycle, and do the calculation in a separate loop. The results need another fifo.

[zyb1003]

Hi,

I think I got what you mean. I did exactly as what said, the DDS sine generator and the arctan2 are in separate SCTL. The Arctan2 has handshaking interface, so do the FIFO.write, so I think push a valid data every 16 cycle is not a problem. However, the problem is if during 1-16 cycle, the data is not valid, then no data will be sent to the FIFO.read, and the program will hang there and fail to run. 

As what I said, anyway to make there's always a data sent to the FIFO.read every cycle, for example, 1-16 cycle first valid data, 17-32 cycle, second valid data. 

Thank you

[nathand · Accepted solution]

I may not have completely understood what you're trying to do, but it sounds like what you want is to wire a 0 (or other small number) timeout to the FIFO read. If the timeout output is true, use the last value (stored in a feedback node). If there isn't a timeout, then use the value from the FIFO and also update the feedback node with that new value.

[dan_u]

You can change the configuration of the atan2 function to have a throughput of 1 cycle/sample. The latency will still be 16 cycles (or whatever your word length is), but you can feed in a new sample at each iteration, and you'll get back data at each iteration (after 16).

If the latency is an issue a look-up table (as Wiebe suggests) might be a better approach.