Problems synchronizing FPGA to PXI clock

[DShadd]

I have recently received several of the new larger FPGAs, the PXI-7813R and the PXI-7833R. It appears that we are unable to reliably synchronize them to the 10 MHz PXI back-plane clock. We have only seen this problem with the newer FPGA boards and did not observe it with either the PXI-7811R and PXI-7813R in the same PXI-chassis. Has anybody else had this problem with the new boards? Synchronization is critical because we are feeding the FPGAs signals from a 40 MS/s ADC and if the ADC clock and FPGA clocks are not the same frequency we see glitches/missed ADC samples. Typically we use the 10 MHz output from the back of the signal generator (that provides the 40 MHz ADC trigger signal) to provide a 10 MHz input with the PXI chassis.

[Prashanth]

Hi Dshadd,

We are not aware of any issues with the synchronization of these new FPGAs (PXI-7813R and PXI-7833R) with the PXI back-pane clock. How are you determining that the synchronization between the FPGA and the back plane is unreliable? How is your hardware setup?

Regards,

Prashanth

[DShadd]

First I should say that the problem is now resolved. It was fixed after we cycled the power on the PXI system after attempting to download the "synchronize" option several times. The first time we cycled the power it did not fix the problem despite leaving the power off for >20 seconds, so the solution hardly seems reliable.

As for the evidence for lack of synchronization, initially we suspected a lack of synchronization as we observed "glitches" on the output of a digital phase-locked loop. The second clue was that the DPLL was actually locking to a slightly different frequency than it should have by about 5 ppm. All other FPGAs in the same PXI chassis were locking to the correct frequency.

We then wrote custom vi's that would cause one FPGA to generate a 40 MHz boolean on-off output on the digital front panel output. This was then looped to the FPGA under test (using the approporiate SCSI cable), which would read out the boolean at 40 MHz and register a missed count every time the boolean value did not change (exclusive-or between the current digital input and the previous input). Any given pair of FPGAs would give us zero unsynched counts, except when the suspect, unsynchronized one was used. The unsynched FPGA missed several thousand counts in a matter of seconds.

Notably, we had this problem with 2 different FPGAs in 2 different PXI chassis. In one case it was the 7833 that was the problem and the 7813 worked fine. In the other system a (different) 7813 was the problem and the 7833 synched fine. We have two more FPGAs waiting to be installed and I will post back here if I see any more issues. We also have three 7811s and three 7831 none of which had synch problems.

Once the synchronization problem was fixed it has not reappeared again which is good news for us.

Thanks,
Daniel

[lightmiddle]

DShadd:

In your post you mentioned that "We then wrote custom vi's that would cause one FPGA to generate a 40 MHz boolean on-off output on the digital front panel output."

I am new to Labview FPGA and could you please tell me how to write a vi to generate a datastream using 7833R?

[Prashanth]

Hi Lightmiddle,

One way to generate a boolean bit stream is to place a whileloop and toggle a boolean constant inside the whileloop and pass that data to the next iteration through a shift register.

I highly recommend anyone starting with LabVIEW FPGA to go through the training material linked below. Its a must if one wants to learn LabVIEW FPGA programming. https://learn.ni.com/learn/article/getting-started-with-fpga

Regards,

Prashanth

[wiebe@CARYA]

A solution can be find here:

https://forums.ni.com/t5/LabVIEW/fpga-synchronize-clock/m-p/678574?jump=true

At least it worked for me.

Wiebe.