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PXIe-7972 DRAM Timing Issue

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Hi,

 

I am having an issue with the memory request data and retrieve data nodes inside a single timed loop. Basically I am attempting to transmit a large array of u64 bit numbers (up to 4,000,000 elements) at 150MHz using both the rising and falling edges of the clock.

 

The issue I am seeing is that while I can get the array of numerics from the PC using a FIFO and store to DRAM, I cannot read it out of DRAM fast enough to transmit. Often getting invalid data or not ready for input back from the memory nodes, I appreciate that DRAM is external memory and therefor cannot necessarily be accessed within a single timed loop cycle. 

 

But if anyone could suggest a way of getting around this issue, or alternative method, it would be greatly appreciated.

 

Attached is the FPGA code I am using.


Thanks.

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Accepted by topic author Nick92

If you're just using DRAM as a temporary storage, you might want to look into using the DRAM FIFO instrument design library which I think does a good job of abstracting a lot of the implementation details with DRAM (as long as you are truly using DRAM like a queue). Some things that I've done that might help.

 

  1. I've put the DRAM reads into a completely separate loop running at the DRAM clock rate and fed that output into a target scoped FIFO. The DRAM api lets you request multiple addresses and you can run the request/retrieve at 166MHz for the 797X series FlexRIOs which I thought worked better than trying to do the request/retrieve inline.
  2. I don't know what FPGA you're using but you don't get the advertised DRAM read/write speeds unless you are using the maximum allowable bandwidth. Even if you're only using 64bits at a time, if you are able to bundle 8 64-bit elements together and only retrieve a new element every 8th iteration you reduce you're required read speeds by quite a bit (meaning it's a lot less likely that you won't have data available).
Matt J | National Instruments | CLA
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