04-07-2021 12:41 PM
Hi,
I am having an issue with the memory request data and retrieve data nodes inside a single timed loop. Basically I am attempting to transmit a large array of u64 bit numbers (up to 4,000,000 elements) at 150MHz using both the rising and falling edges of the clock.
The issue I am seeing is that while I can get the array of numerics from the PC using a FIFO and store to DRAM, I cannot read it out of DRAM fast enough to transmit. Often getting invalid data or not ready for input back from the memory nodes, I appreciate that DRAM is external memory and therefor cannot necessarily be accessed within a single timed loop cycle.
But if anyone could suggest a way of getting around this issue, or alternative method, it would be greatly appreciated.
Attached is the FPGA code I am using.
Thanks.
Solved! Go to Solution.
04-08-2021 08:44 AM
04-08-2021 02:44 PM
If you're just using DRAM as a temporary storage, you might want to look into using the DRAM FIFO instrument design library which I think does a good job of abstracting a lot of the implementation details with DRAM (as long as you are truly using DRAM like a queue). Some things that I've done that might help.