PXI RT system: timing of data acquisition in control loop

[matthias.richwin]

Hi all,

I am quite new to RT systems, although I feel confident with Labview.

We have a new system, a PXI-8108 controller and a PXI-6221 M series daq card.

I am trying to set up a small real time control loop, reading one analog input voltage, one counter input (quadrature), and writing the duty cycle of a PWM signal on the other counter. The loop should run at 20 kHz, which should also be the sampling rate of the inputs. To accomplish this, I have set the analog input to hardware trigger and used the IO task as the timing source for the timed loop.

I have attached the sample project, where everything has been removed except for the IO tasks and some simple instrumentation to measure the timing.

I see that the timed loop runs at a frequency of about 10 kHz, instead of 20 kHz, and I do not understand why since the timing of the IO tasks seems not critical (3-5 µs each).

Another striking thing is the fact that I have to wait for one PWM period to complete before I can set a new duty cycle. This makes me change the PWM frequency from 20 kHz to 25 kHz and introduce an additional delay so that the cycle has time to complete. I believe that if the timing of the loop would be ok, this would not be needed as well.

And: Sometimes it happens that the timing of the whole thing goes totally mad, with great jitter in one or two of the IO tasks (up to 30 µs then). But I cannot reproduce that.

Could any of you gurus look into my code?

Thanks a lot.

Matthias

[christian_w]

I suggest you to monitor the CPU load first. This should be possible via the VGA output.

Obviously you create a timing violation.

br

Christian

[matthias.richwin]

Hi,

thanks for your reply. I see

CPU 0: 75%

CPU 1: 8%

Should be ok, or?

Regards

Matthias

[christian_w]

CPU load should be ok.

I haven't used Timed Loop with Frames so far, but I suggest to use an internal timing source. A dt of zero looks real strange for a timed loop.

From  the LV Help

When the Wait Express VI runs inside a timed structure or a VI set to time-critical priority, it blocks the execution of all other code in the same timed structure or VI because timed structures and time-critical VIs are single-threaded.

Try to setup your timing without this wait express VI.

br Christian

[matthias.richwin]

Hi,

thanks for pointing that out!

The "zero" dt should just mean that the timed loop starts immediately when the connected timing source generates the next tick. But I have now replaced it with the internal 1 MHz clock and set the period to a suitable value in µs. This also allows me to use frames in the timed loop and to specify the relative start time of the second frame, where now the PWM output resides.

This yields at least a stable behavior at 10 kHz.

Thanks!

Matthias