Optimizing Serial protocol implementation in LabVIEW FPGA

[Bharathi]

Hello everyone,

I have implemented the serial protocol to transmit and receive messages on NI PXI - 7831 R card. On compilation the FPGA VI nearly took 70% of the resources on board. The following is the device utilization summary.

Device utilization summary:

Number of External IOBs 96 out of 324 29%
Number of LOCed External IOBs 96 out of 96 100%

Number of RAMB16s 4 out of 40 10%
Number of SLICEs 3628 out of 5120 70%

Number of BUFGMUXs 1 out of 16 6%

This just forms a small module in my main application. I would like to know is there any way to optimize the serial protocol design in the FPGA card
. In case, if the optimization is difficult, i really suspect if the NI - PXI 7831 R FPGA card can be used for larger applications!!

Thanks,
Subramania Bharathi. R

[mrak1]

Hi Bharathi,

There are many ways to optimize a LabVIEW FPGA application and I don't think that I can help you without seeing your code. However, here are some general tips.

• Minimize usage of arrays or clusters - each bit in an array or cluster consumes about 2 slices where a bit in a normal control or indicator consumes about 1.2 slices.
• Combine multiple indicators and controls - For example, if you have four U8 indicators, use the "Join Numbers" primitive to combine them into a single U32.
• Shared Resources - SubVIs, Local Variables, Device IO nodes, Interrupts, etc. - multiple instances of the same item on the diagram can invoke extra arbitration
• Arbitration Options - Set the arbitration options according to your needs on the D
  IO lines. Doing this can save you a considerable amount of space.
• Consider the Single Cycle Timed Loop - Advanced Feature - There are several restrictions when using this structure, but the benefits include savings in space on the FPGA chip and execution time.

I hope that this gives you some ideas.

Mike

[mrak1]

Hello again..

A couple clarifications on arrays.... Sometimes arrays are extremely useful in LabVIEW FPGA. Here are two use cases where they should be used:

• Temporairly combining elements into an array:
  • Allows you to use a single primitive, such as the Add function, on a series of values.
  • As long as the whole array is not placed into a control or indicator, it is just a series of wires on the FPGA chip and doesn't consume additional space.
• Arrays or clusters with less than or equal to 32 bits total (i.e. 2 element array with I16s, 32 element boolean array, or cluster with 4 I8s) elements do not consume more space on the FPGA than a normal control or indicator.

I hope that this helps,

Mike

[Bharathi]

Hi mike,

Thanks for your immediate response.
I have attached the serial protocol FPGA VI that i have implemented in NI-PXI 7831 R Card.
I just modified the example codes FPGASerialRead.llb and FPGASerialWrite.llb to suit my application.
The following is the link to the above libraries.

http://sine.ni.com/apps/we/niepd_web_display.DISPLAY_EPD4?p_guid=C1074FF79B533B59E034080020E74861&p_node=200449&p_submitted=N&p_rank=&p_answer=&p_source=External

It would be of great help if you could suggest me some changes to optimize the VI

Thanks
Subramania Bharathi. R

[mrak1]

Hi,

Can you send your LabVIEW FPGA Project File? I would like to see that as well.

Thanks,
Mike

[Bharathi]

Hi Mike,

I could not understand what a LabVIEW Project File is.
Is that the host VI you are talking about?

Bharathi

[mrak1]

Are you using LabVIEW FPGA 7.1? LabVIEW FPGA 7.1 requires an additional file named the Embedded Project File ( *.lep) for defining the IO for the device. If you are using LabVIEW FPGA 1.0, then this does not exist and don't worry about it.

[Bharathi]

I am using LabVIEW 7.0 and LabVIEW FPGA 1.0. I would be pleased if you could give your e-mail id, so that i can contact you directly also!

[Bharathi]

Hi mike,

I have modified the code according to the changes you had specified but still i find it difficult to optimize to a sufficient level to suit my application.
Awaiting your response.

Thanks
Bharathi.