I am try to run the CAN Signals Transmit.lvproj on the CompactRio and everytime I try to compile the FPGA vi I get the follwowing error.
LabVIEW FPGA: The compilation failed due to a Xilinx error.
Details:
ERROR: [Synth 8-1031] cincorrectmodule is not declared [/opt/apps/NIFPGA/jobs2/m5073RX_sfJkTuU/Slot_1.vhd:6637]
INFO: [Synth 8-2810] unit behavioral ignored due to previous errors [/opt/apps/NIFPGA/jobs2/m5073RX_sfJkTuU/Slot_1.vhd:6555]
INFO: [Synth 8-2810] unit propertycontrolp1slot_1 ignored due to previous errors [/opt/apps/NIFPGA/jobs2/m5073RX_sfJkTuU/Slot_1.vhd:7080]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1016.527 ; gain = 179.285 ; free physical = 27812 ; free virtual = 29423
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
9 Infos, 4 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
::RTL Elaboration failed
while executing
"source -notrace ./.Xil/Vivado-17192-ip-10-0-53-103/realtime/toplevel_gen.tcl"
invoked from within
"synth_design -keep_equivalent_registers -top "toplevel_gen" -part "xc7k70tfbg676-1" -flatten_hierarchy "full""
(file "/opt/apps/NIFPGA/jobs2/m5073RX_sfJkTuU/synthesize.tcl" line 21)
invoked from within
"source "/opt/apps/NIFPGA/jobs2/m5073RX_sfJkTuU/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Mon Jun 4 12:57:49 2018...
Compilation Time
---------------------------
Date submitted: 04 Jun 2018 14:57
Date results were retrieved: 04 Jun 2018 14:58
Time waiting in queue: 00:45
Time compiling: 00:28
- Generate Xilinx IP: 00:00
- Synthesize - Vivado: 00:11
