Mutex or semaphore functionality for FPGA?

[RonW]

How do I protect a read-modify-write region in the FPGA while allowing the variable to be updated externally outside of that region? The FPGA synchronization palette doesn't have semaphores, and I can't create a single-element FIFO in the FPGA.

[RonW]

I created a mutex using a one-bit memory block, and a non-reentrant VI.

The VI loops as long as that bit is set, then sets it and exits. Calling this VI is equivalent to setting a mutex (or being blocked on it). Clearing the bit is equivalent to unblocking the mutex.

So the first call to the VI sets the bit and exits.

The second call waits in the VI because the bit is set.

The third call waits to enter the VI because the VI is not reentrant.

The first caller clears the bit.

The second call exits the VI because the bit is clear, but the VI sets the bit.

The third caller enters the VI...

ad infinitum.

Now if only it would compile without telling me "Illegal combination: Port A Width and Port A Depth".

[Van_L]

Message Edited by Van_L on 03-06-2008 07:25 PM

[Van_L]

Hi Ron,

Sorry for the late reply,
I have never seen this error message before therefore I was doing more reasearch on this before I can post an legitimate reply.

Your implementation of semaphore looks logical and should obviously work. I think the problem lies in the mutex you have created.
It seems like Xilinx doesn't support one-bit memory block (depth = 1 in memory block)

Can you try to use other "registers" to store this mutex as locals: globals, fifos, feedback nodes, etc...

Let me if how this works.