Multiple FPGA DMA FIFO writes

[kmc]

I have two timed loops which are running on an RT PXI which both need to write to an FPGA DMA FIFO.  Is there synchronization within the Invoke Method of the FPGA reference when there are multiple writers which would make my timed loops non-deterministic.  For example, if I split the FPGA reference wire and passed it to the two loops and then each called the DMA FIFO write, could one loop potentially block the other?  If they do block, is this best way to achieve what I want to do, to make a third loop which contains the FPGA reference and have the other two loops pass messages to it via seperate RT FIFOs?  For example, the third loop would read a message from the 1st loops FIFO, write it to the DMA FIFO, and then read the 2nd loops FIFO and write the message to the DMA FIFO.

thanks in advance,

kmc

[CyGa]

Hello !

I think that might find some answers here : http://zone.ni.com/reference/en-XX/help/371599C-01/lvfpgaconcepts/arbitration_options/

[kmc]

Thanks for the response,

So if my DMA FIFO is setup for Never Arbitrate, then I need to control access to the DMA resource.  It seems that choosing any of the other options would make my timed loops non-deterministic.  Is the method which I described, having a third loop containing single access to the DMA FIFO, a reasonable solution for what I need to do or does anyone know of another way.

Thanks again

kmc

[CyGa]

If you think that writing in your FIFO takes too much time that it makes your loopsto be non-deterministic (even if the writing process is quite fast) then you should use two separate FIFOs and then combine them... Another way to use RT FIFO in order to have control onto the time needed to read/write date into the fifo...

[pablosan]

I have the same problem. If you know the solution, can you show me?