How do you normally/want to stop the program(s)?
@fathurrkoesn wrote:
I run the program on Host and set the running conditions of the program on FPGA 2. But, if I Stop FPGA 2, the circuit will be error because it must be stopped via Host.
It sounds like your normal Host.vi (which I guess is not the one in the screenshot - that's the test VI?) would normally pass some signal to FPGA(1), which would then communicate this to FPGA2, which would then stop.
In that case, just do the same - communicate the Stop signal (message, tag, whatever) to FPGA(1), and then let the simulation propagate that to FPGA2.
You can use some other method to stop the While loop in your simulation VI - either a Delay node with a specific delay if you know approximately the number of iterations to stop, or perhaps the error wire from the DENs?
I'm not sure what you mean with this bit:
@fathurrkoesn wrote:
[I] set the running conditions of the program on FPGA 2
so perhaps I'm misunderstanding the post... do you mean you change the behaviour during DEN simulation by altering FP values on FPGA2's main VI? If so, how do you normally (i.e. not in simulation) adjust these values? You could also do that in simulation (if it isn't overly complicated signal patterns that you've already tested work properly).