Labview FPGA optimizing code (reducing resources)

[DatLe]

Hi there,

I am new to this forum and have questions regarding to optimizing FPGA code since I have a very big program. Currently, I need to reduce resources first, and listing the questions here. Some of them are kind of "making sure" question.

- In this link: http://digital.ni.com/public.nsf/allkb/311C18E2D635FA338625714700664816

It says "Eliminate Arrays on the Front Panel", what if I use array without shown up on Front Panel? Does it take a lot of resources?

- Should I change every array in my code to block memory? For array, we can manipulate data, for example rotate 1D array. If I change to block memory, I will have to write all of the manipulations by myself.

- Because the program is big, I wanted to put them in subVIs to make it easier to read, also can reduce loop time when the subVIs run parallely, I want to make sure that this change will not increase the resource? I learnt that indicators on front panel of subVIs don't increase resources consumption.

- Multiplication takes few resources/calculation time than division?

Thanks in advance 🙂

[nathand]

The resources used by an array on FPGA are proportional to the size of the array, so it depends on how large the array is. An array with a single-digit number of elements is probably fine; an array with hundreds of elements is probably not (unless those elements are booleans). Accessing memory elements efficiently requires more work, especially inside single-cycle timed loops, so I would replace arrays with memory blocks strategically rather than trying to replace all of them.

So long as your subVIs are reentrant, there's no penalty for using subVIs. Once the FPGA is compiled there's no difference between code in a subVI and code on the top-level diagram, unless arbitration is necessary to handle access to multiple instances of the same non-reentrant subVI.

Yes, multiplication requires fewer resources than division. See the FPGA Resource Utilization table to get a sense of the difference.

If you share your code, we might be able to provide more specific suggestions.

[Dragis]

The previous post covers the basics well. In the end, it is how you use the arrays that matters. Arrays are great if you are describing parallel code paths where the interleaving and routing of the signals can be described concisely with the array operations. Where arrays use a lot of resources are

(1) when you register them using top-level controls and indicators, feedback nodes, shift registers, etc. and

(2) when you perform operations that are not compile-time statically assigned such as indexing an array with a variable input.

I would also try to program according to the design patterns on the following page. If you follow the guidelines there, you'll get the optimal design on whichever target you end up synthesizing for.

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_array_memory_implement/

[DatLe]

- Thanks guys for the informative posts, the subVI is reentrant as default. I just call this subVI once in the main VI so I guess there's no problem with entrancy/reentrancy. 

- Currenly, I am having a problem with DSP48E as in the pic attached. I changed the compiling option to "Area" instead of "Timing performance" but it doesn't resolve the problem. It is quite weird since I did some little change in the code, and the new code is not too much larger than the old one. The 2nd pic is for the old code, the amount of resources is big, but still in a good range. Even when I tried to delete some more things, the problem still exists. When through this post (http://forums.ni.com/t5/LabVIEW/Large-FPGA-vi-compiled-in-LV-2009-but-not-2010/td-p/1636950) but not sure what should do. Since I thought that high through put math takes more resources than normal math. And because I have a lot of math calculations, changing all of them is not a nice thing to do. 

I am using Labview 2011, cRIO-9118.

[nathand]

You'll probably need to share your code with an NI engineer in order to resolve this, since it appears that the issue is use of a specific FPGA component (a DSP48) rather than with your overall design. You could also go through the Resource Utilization Table to which I linked in an earlier post; your cRIO has an LX110 FPGA, so look at that table. See which functions use a DSP48E and reduce your use of those functions until it fits (you may only need to replace one of them).

[DatLe]

In the past, it always at 100% for DSP48s like you saw. At that time, I added math calculations, and when I compiled, it always increase other resources, let say LUT. That happened many times until I see the strange thing today. I thought that the compiler does an "intelligent" way to compile successfully with the maximum of DSP48s usage by using other resources, but not this time. Looking at Resource Utilization Statistics, likely my code goes to limit of 64. And if with that limit, how many math calculations we can do with NI FPGA devices? Just "a few"!

[nathand]

You might want to follow this thread about the same problem: http://forums.ni.com/t5/LabVIEW/Is-there-an-obvious-way-to-prevent-an-FPGA-multiply-from-using/m-p/2...