LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

Labview FPGA: how to change array size in a loop without generating errors

Solved!
Go to solution

Hi, guys! I'm new to labview fpga. Basically I would like to build a VI for convolution. However in fpga it seems like the Array size can not be changed at all. My VI works fine in the main VI but it just keep reporting errors in fpga. So how to actually insert elements into Arrays in a for loop. Or how to build a VI for convolution in fpga. Thank you very much! 

0 Kudos
Message 1 of 9
(2,818 Views)

Hi rwthybw,

 

Or how to build a VI for convolution in fpga.

Use fixed-sized arrays - the FPGA only supports them. Point.

 

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
0 Kudos
Message 2 of 9
(2,813 Views)
Solution
Accepted by topic author rwthybw

Hi rwthybw,

Could you use the on-board memory for your FPGA device instead of an array?

Steve

0 Kudos
Message 3 of 9
(2,805 Views)

this is the first part, however I eventually would like to perform discrete wavelet transform in fpga which requires decimation. I can use fixed-size in convolution but the decimation will definitely to change the array size.

0 Kudos
Message 4 of 9
(2,786 Views)

Hi! I didnt try yet, I will do it. And could you shortly describe the function of the Memory in fpga ? Thank you!

0 Kudos
Message 5 of 9
(2,785 Views)

This is good starting point for FPGA Memory Items.

 

0 Kudos
Message 6 of 9
(2,783 Views)

Can you explain why you need to insert elements into arrays to perform a convolution? There are efficient in-place algorithms. Can you show us what you are doing, i.e. some simplified code? Thanks!

0 Kudos
Message 7 of 9
(2,766 Views)

Hi! I'm sorry my Supervisor told me I'm not allowed to upload the code online, though I don't think what I'm doing is classified.

Anyway I have successfully built the convolution with fixed size Array. However the Problem is that I'm trying to build discrete wavelet transform which contains decimation of the samples. So basically, at the end of the For Loop, I need to discard half of the samples and return the half size Array to the beginning. So the shift Registers at my For Loop have different size and the fpga does not allow this. That's my problem now.

 

Thank you!

0 Kudos
Message 8 of 9
(2,741 Views)
Solution
Accepted by topic author rwthybw

Hi rwthybw,

 

I need to discard half of the samples and return the half size Array to the beginning. So the shift Registers at my For Loop have different size and the fpga does not allow this.

You could:

- replace half of the array elements by zeros…

- reorder the needed array elements to the first half of your array and replace the second half by zero…

- use a 2nd shift register to keep the half-size array

All those options boil down to: you have to work with fixed-sized arrays!

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
0 Kudos
Message 9 of 9
(2,737 Views)