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LabView IDE uses only 25 percent of CPU

Hello,

 

while compilation in LabView 2016, the LabView IDE uses max. 25% of the CPU (I use a machine with 4 cores but only 25% of the whole CPU are used).

 

Question:

Can I use e.g. 80% .. 90% of the whole CPU (e.g. use 3 cores) ?

 

This would make the compilation process faster (currently it need ~15 minutes)

 

Thanks

EW

My System:

 

MySystem.jpg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU usage:

 

Task_mgr_processes.jpg

 

 

Task_mgr_CPUs.jpg

 

LV_Compilation_Max_25_percent.jpg

 

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Eugen Wiebe
Bernstein AG
CLAD - Certified LabView Associate Developer
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From my basic understanding of compilers in general, they tend to be linear in nature.  This means parallelization is not really possible.  So maxing out a single core is probably the best you are going to get.



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@crossrulz wrote:

From my basic understanding of compilers in general, they tend to be linear in nature.  This means parallelization is not really possible.  So maxing out a single core is probably the best you are going to get.


... It is not as if the compiler is written in LV where parallel threads come easy.

 

Imagine a compiler with a race condition where it never generated the same code twice... HOLD IT! Isn't that what happens with FPGA code?

 

Smiley Wink

 

Ben

 

 

Retired Senior Automation Systems Architect with Data Science Automation LabVIEW Champion Knight of NI and Prepper LinkedIn Profile YouTube Channel
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@Ben wrote:

... It is not as if the compiler is written in LV where parallel threads come easy.


It's not just what the compiler was written in.  It is the algorithm(s) used for compilations tend to be serial operations.  Even with Vivado (Xilinx FPGA compiler), only parts of the compiler can utilize multiple cores.  Here is an interesting discussion about this in the LabVIEW FPGA Idea Exchange: Multi-core Compiling.  One of the NI folks even chimed in stating that it is only the place and routing that can can be parallelized.  Synthesis (possibly the longest part of the compile process for FPGA) is still a serial operation.



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