LabView 2020 FPGA Disable Structure

[Edmund130]

The new LabView 2020 Disable Structure seems to act completely differently from previous Disable Structures that only included Enable and Disable.  Now it includes Compiler constants that refer to Simulation modes, Operating System type, Windows version, etc., ...  However in the projects>Properties section I can set Conditional values, but it seems to have no effect.  

I am using an NI Example for FPGA SPI, and critical input and output structures are using a Disable Structure to block real hardware connectivity to the outside world and only use Simulation controls and indicators.  The version I want is the "Default" which contains the real connections to the outside world.  Yet nothing I do seems to effect the Disable Structure and permit me to use the "Default" Value instead.

The name of the NI Example is:  "FlexRIO - NI SPI FPGA Simulation"

[Intaris]

Sounds like "Conditional Disable", not "Disable Structure"

[crossrulz]

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@Edmund130 wrote:

The new LabView 2020 Disable Structure...

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The Conditional Diagram Disable Structure has been around since at least 8.2 (oldest version I can verify).

As to the rest of your issue, I am not seeing that example.  Was this from a separate install and not just FlexRIO?

[Edmund130]

This is the FPGA Target Diagram for NI Example:  FlexRIO - NI SPI FPGA Simulation and Real IO - FPGA.vi  However as you can see the FPGA_EXECUTION_MODE == DEV_COMPUTER_SIM_IO only evokes simulation, not real world connectivity.  The Projects>Properties does not seem to permit me to change this Environment constant or control the FPGA_EXECUTION_MODE.

[crossrulz]

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@Edmund130 wrote:

The Projects>Properties does not seem to permit me to change this Environment constant or control the FPGA_EXECUTION_MODE.

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That is a build-time variable.  It is just like when I use the "Runtime_Engine == True" case for my applications.  I cannot run that case in the development environment, but is compiled into the executable.  In this case, the FPGA_EXECUTION_MODE is set to something else when you compile your FPGA.

[Edmund130]

How do I control the FPGA_EXECUTION_MODE value?  And how can I confirm that the value changed or is invoked?

[Edmund130]

How does the FPGA Compiler know I do not want to run in simulation mode?   But real FPGA Target Mode?

[billko]

Under your project's properties, you'll see this:

This is where you set the conditionals.  Note that this is set during development and the FPGA gets compiled with those symbols and values.

Edit: I saw that you said you looked in the project's properties.  Is this what you said you couldn't change?

[Edmund130]

No matter what I changed the only enabled feature was the one that I did not want.  Nothing in the Conditional Structure changed int he source code.  all the other options are grayed out.

[Terry_ALE]

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@Edmund130 wrote:

How do I control the FPGA_EXECUTION_MODE value?  And how can I confirm that the value changed or is invoked?

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See https://www.ni.com/docs/en-US/bundle/labview/page/lvhowto/creating_cond_disable_struc.html

The FPGA_EXECUTION_MODE tag is automatically set when you right-click on the FPGA target and select "Select Execution Mode".

I recommend against setting this tag in the Target >> Properties page under Conditional Disable Symbols.