LabVIEW FPGA VI execution mode vs single cycle timed loop or high throughput math nodes

[bn698]

Hello Internet,

I am having a bit of a trouble with LabVIEW FPGA. I implemented an algorithm the fpga of a sbRIO. The algorithm itself does not rely on any specific timing relationship, just processes the input sample in each iteration. For performance and resource optimization, I use high-throughput dsp nodes and single cycle timed loops. The problem is that I get different results when running the fpga VI on the development computer and when running it on the fpga itself. The input signal is a constant 1 value, which is literally a numeric constant in the VI.

Do you guys have any idea that I may fail to know about executing VIs on the dev computer. I know that there may be timing differences, but the code should work exactly the same way as it would on the fpga.

Any suggestions are welcome,

Norbert

[ToeCutter]

Post us some simple code that demonstrates the problem.

[david1147]

They should act the same. Which node are you using and what are the different results? Any screenshot or code would be of help.

[bn698]

Thanks for the replies.

I understand my description was quite general.

I'm still trying to create a VI that demonstrates the problem in a simple scenario. Until then I am posting the project in its current state. If you guys could have a look at it and see if you can spot out anything that can be a cause for different functioning between the VI execution modes (on dev pc and on fpga), I would be grateful. I don't want you to spend on it any more than like 5 minutes, just take a look at it if you can.

Wht the code does is basically a recursive 16 point DFT. The input signal is a constant value of 1 (labeled s(n) in the code), so the elements of the "Spectrum" output array should be all zero, except for the first one. This happens when the execution mode is dev computer. After the 16th iteration the spectrum array is (there is an initial transient due to the nature of the algorithm):

0.999512; 0; 0; 0; 0; 0; 0; 0; 0; 0; 0; 0; 0; 0; 0; 0

When the code runs on the fpga, the spectrum array settles to the following array:

5.65674; 1.71533; 1.9585; 1.49365; 0.376953; 1.02295; 4.05859; 4.00684; 3.99951; 5.65674; 5.65674; 4.34863; 4.54639; 5.65674; 5.65674; 4;31348

I don't understand where this difference comes from. Any ideas are welcome.

Thank you in advance,

Norbert

[Dragis]

In theory they should produce the exact same results. Glancing at the code I don't see anything obvious that would be causing an issue. It might be helpful to unit test each of those top-level blocks and make sure they separately match between hardware and desktop execution. That might help narrow down which block is causing an issue.

[david1147]

I tried this on a 7966R (Virtex 5) target, and the results after 16 iterations are the same. Seems like a fpga family specific issue (Spartan 6). You can try to change the "Implementation Resource" of all Multiply and Complex Multiply to "Look-Up Table" to have another try.

[ValkoA]

Dear Norbert,

I tested your code in simulation and got the same results (the correct ones). so the issue lies within the FPGA bitfile. What I would advise is to create a DMA to your host, and stream the outputs from each of your subVI at every iteration. From that data, you should be able to find were the error happens, as well as when it happens (as it might have to do with initialisation).

Please let us know your results.

Kind regards:

[david1147]

Some update on this thread:

I finally got a chance to run the VI on a Spartan 6 target, and I observed the same correct result.

I would agree with ValkoA that you could use DMA FIFO to pass all the data to host for a thorough investigation if you are interested.

[bn698]

Hey Guys,

Thank you for all the valuable help. I have been quite busy recently, but I hope I'll have more time to deal with the issue as the holidays come. I'll keep you updated.

David, you have executed a code on a Spartan6 target, and got the correct results? That's interesting. What implementation resource option did you specify for the multipliers?

Andris, congrats on your CLA 🙂

[david1147]

>> David, you have executed a code on a Spartan6 target, and got the correct results? That's interesting. What implementation resource option did you specify for the multipliers?

Yes. I didn't change the implementation resource of the multiplier nodes and just wanted to reproduce the incorrect behavior. I added an "x" control to the VI, compiled it and set the x value to 16. I now see the correct result. I'm using LV FPGA 2013 with ISE 14.4, by the way.