I am experimenting with LabVIEW FPGA and Vivado Design Suite. I haven't found any threads or whitepapers on this topic so far.
I am trying to integrate simple block design created in Vivado into LabVIEW using IP Integration node.
For test I am trying with simple design: just simple binary clock in diagram (block design picture attached, complete project attached).
For this example I try to make everything work in simulation for start for FlexRIO target PXIe-7975R with Kintex7.
From LabVIEW project I saw that device chip is xc7k410tffg900-2 and I crated my Vivado project for that device.
After finishing block design in Vivado I created wrapper and did synthesis. I exported netlist (.edn file) and this is where I am stuck.
I am trying to put this .edn netlist as top level file in IP integration node (picture attached) but I am not able to make much progress.
At page 3 (generate support files) when I press Generate button it starts doing something but at end I get this message (full log attached as txt):
I restricted core to Kintex7 but same error happens when it is not restricted.
"Generated IP unsuccessfully. Your source file(s) can't work for the FPGA families) you select. Fix the above error(s) or warning(s) and generate the IP again, or go back to previous page to reselect FPGA Family Support."
I have these questions:
Is .edn netlist file aproach correct for this?
- If it is, what could I be doing wrong?
- If it is not, what is correct way (do i need some additional vhdl wrappers)?
I am using LabVIEW 2020 64bit with FPGA module and corresponding Vivado compilation tools (2019.1)