LabVIEW FPGA IP Integration: Integrate Xilinx Vivado Block Design

[VukObradovic]

Hello everyone,

I am experimenting with LabVIEW FPGA and Vivado Design Suite. I haven't found any threads or whitepapers on this topic so far.

I am trying to integrate simple block design created in Vivado into LabVIEW using IP Integration node.

For test I am trying with simple design: just simple binary clock in diagram (block design picture attached, complete project attached).

For this example I try to make everything work in simulation for start for FlexRIO target PXIe-7975R with Kintex7.

From LabVIEW project I saw that  device chip is xc7k410tffg900-2 and I crated my Vivado project for that device.

After finishing block design in Vivado I created wrapper and did synthesis. I exported netlist (.edn file) and this is where I am stuck.

I am trying to put this .edn netlist as top level file in IP integration node (picture attached) but I am not able to make much progress.

At page 3 (generate support files) when I press Generate button it starts doing something but at end I get this message (full log attached as txt):

I restricted core to Kintex7 but same error happens when it is not restricted.

"Generated IP unsuccessfully. Your source file(s) can't work for the FPGA families) you select. Fix the above error(s) or warning(s) and generate the IP again, or go back to previous page to reselect FPGA Family Support."

I have these questions:

 Is .edn netlist file aproach correct for this?

 - If it is, what could I be doing wrong?

 - If it is not, what is correct way (do i need some additional vhdl wrappers)?

I am using LabVIEW 2020 64bit with FPGA module and corresponding Vivado compilation tools (2019.1)

[John80]

I have done this before:

* Create a wrapper vhdl file that instantiates your ip

* From IP Integration Node add both your wrapper .vhd file and your netlist (.edn) / checkpoint (.dcp)

* Set your wrapper .vhd file to be the top-level

file: design_1_wrapper_wrapper.vhd

--Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
--Date        : Tue May  9 20:22:00 2023
--Host        : Ryzen10 running 64-bit major release  (build 9200)
--Command     : generate_target design_1_wrapper.bd
--Design      : design_1_wrapper
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper_wrapper is
  port (
    A_0 : in STD_LOGIC;
    B_0 : in STD_LOGIC;
    Cin_0 : in STD_LOGIC;
    Cout : out STD_LOGIC;
    S : out STD_LOGIC;
    dout_0 : out STD_LOGIC_VECTOR ( 2 downto 0 )
  );
end design_1_wrapper_wrapper;

architecture STRUCTURE of design_1_wrapper_wrapper is
  component design_1_wrapper is
  port (
    A_0 : in STD_LOGIC;
    B_0 : in STD_LOGIC;
    Cin_0 : in STD_LOGIC;
    dout_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    S : out STD_LOGIC;
    Cout : out STD_LOGIC
  );
  end component design_1_wrapper;
begin
design_1_i: component design_1_wrapper
     port map (
      A_0 => A_0,
      B_0 => B_0,
      Cin_0 => Cin_0,
      Cout => Cout,
      S => S,
      dout_0(2 downto 0) => dout_0(2 downto 0)
    );
end STRUCTURE;

and here is my block design wrapper (that should be included as part of the checkpoint)

--Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
--Date        : Wed May 10 12:47:54 2023
--Host        : Ryzen10 running 64-bit major release  (build 9200)
--Command     : generate_target design_1_wrapper.bd
--Design      : design_1_wrapper
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
  port (
    A_0 : in STD_LOGIC;
    B_0 : in STD_LOGIC;
    Cin_0 : in STD_LOGIC;
    Cout : out STD_LOGIC;
    S : out STD_LOGIC;
    dout_0 : out STD_LOGIC_VECTOR ( 2 downto 0 )
  );
end design_1_wrapper;

architecture STRUCTURE of design_1_wrapper is
  component design_1 is
  port (
    A_0 : in STD_LOGIC;
    B_0 : in STD_LOGIC;
    Cin_0 : in STD_LOGIC;
    dout_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    S : out STD_LOGIC;
    Cout : out STD_LOGIC
  );
  end component design_1;
begin
design_1_i: component design_1
     port map (
      A_0 => A_0,
      B_0 => B_0,
      Cin_0 => Cin_0,
      Cout => Cout,
      S => S,
      dout_0(2 downto 0) => dout_0(2 downto 0)
    );
end STRUCTURE;