LabVIEW FPGA Error -61003

[kuroro_W]

I am using a cRIO NI‑9054 to generate a communication frame signal using the FPGA.

Each bit is composed of three states of 600 µs each:

• Start: 600 µs at logic 1
• Data: 600 µs at logic 0 or 1 depending on the bit value
• Stop: 600 µs at logic 0

I am using the attached VI to generate this signal. The VI is placed inside a Timed Loop that reads the elements to send from a DMA FIFO and passes them to the VI to generate the output signal.

However, when I compile the FPGA, I get the following error:

Can anyone tell me why this piece of code produces this error?

Regards

[GerdW · Accepted solution]

Hi kuroro,

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@kuroro_W wrote:

Can anyone tell me why this piece of code produces this error?

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As the error message says: you cannot use FPGA IO nodes inside a FOR loop, when that FOR loop is placed within a SCTL…

Two options:

1. Don't use a SCTL to output your bits.
2. Create code that follows all the rules for SCTLs and FPGA IO nodes.

[kuroro_W]

Hi GredW,

Thank you for your reply.

The error message was indeed clear, but it was pointing to every function inside the For loop (even the wait), which I found unusual. Since I’m new to FPGA development in LabVIEW, I couldn’t immediately identify the root cause.

After doing some research, I now understand that the code violates some SCTL rules. Thank you for pointing that out.

Regads,