LV UDP read blocks VISA read (com-port)

[Stephan112]

Hello,

after searching the web and Labview help/examples I still have no solution for my problem…

Problem description:

One VI that reads UPD packages from an FPGA via Network (Ethernet) and a second VI that reads data from a COM-port both are running on a NI-PXI System under LV 2025 Q1.

As soon as I start the UPD read function in a loop the VISA read does not return any message (empty string).

The VISA read does not show an error.

As soon as I stop the UPD-stream (exit the read UDP loop) the read VISA function starts to generate messages as expected.

The sequence of starting the stream does not matter. If the VISA-read function is running and the UDP-read is started VISA is blocked. If UDP is already running and VISA is started the output string is empty from the beginning. But no error is thrown in both cases.

To make it clear UDP-read and VISA-read do NOT run in the same VI in different loops but in two separate Vis. I have no idea why UDP-read blocks VISA-read. The VISA VI runs as expected if the UPD VI is not started.

An answer would be appreciated.

[Kyle97330]

Hi Stephan, welcome to the forums.

Can you post the two VI files containing the loops in question?  And can you save them to an earlier version before you do so?

Most of us on the forum want to see the fine details of the problem instead of broad descriptions.

Also, most of us don't update to the most recent LabVIEW version.  I personally am on 2021, others are on other versions.  I recommend saving back to 2019 to give a good chance that anyone who wants to look at your code the ability to do so.

It might also help to post your exact hardware setup, i.e. model numbers, instead of just saying "a NI-PXI system".

[Martin_Henz]

Beside the good recommendations from Kyle97330:

You are transmitting UDP packets directly from your FPGA board?

It is not totally impossible, but need lot of hours to implement and a lot of FPGA space. This sounds wrong to me. Did you really implement a UDP stack on your FPGA hardware?

What I really want to say: Please always be very specific and very exact or describe what you want to do and post your code (or a simplified example).

[Stephan112]

Hello Kyle,

thanks for the fast response. To start with the good news: the problem disappeared over night.

The day before I did 2 or 3 re-starts of the PXI but it did not help. Next day I prepared the two simplified Vis as you requested and tested if these Vis show a similar problem. But they were running fine (both streams UDP and VISA were working). The major difference to the original VIs was that I added some data manipulation in the VISA read loop. So, I added step-by-step the data analysis functions and tested each step – still working. Finally, I started the original VIs without any changes, and they were running. It might be a problem with my hardware… If I find the problem, I will update the post.

For the sake of completeness here the details of my system:

PXIe-1092 with Xenon CPU E3-1515M v2 2.8 GHz; Win 10 IoT Enterprise; Intel Ethernet Connector l219-LM

Device is connected via 20 m Ethernet cable (UDP); a 20 m active USB3 cable with a hub and a RS422 to USB converter with FTDI chip set (VISA).

PS: makes no sense to attach the Vis as they do not show the problem.

Stephan

[Stephan112]

Hello Martin,

thanks for your fast feedback.

yes, I must use an external FPGA-Board to establish communication between my device and a PC. But the FPGA is not the cause of the problem. I have checked the UDP communication also with a second PC as UPD package sender and it showed exactly the same behavior.

For the implementation of the UPD protocol on the FPGA there are quiet a lot of usable libraries (IP) available for my hardware.

As I already wrote to Kyle: the problem solved itself. But I will try to find the root cause and will keep you updated. I always want to understand what went wrong.

Stephan

[billko]

I'd be terrified it could happen again at any time.  I hope you find the root cause.

[Stephan112]

Hello,

and thank you for the feedback. Now, the problem is there again overnight… but I have found an issue that can explain the problems I had/have – as least partly.

It is related with an intensity graph in the first VI and a property node in the second VI.

“UDP-VI”:

In the first VI I continuously update an intensity graph with an U16 2D array (~50 fps) the graph is scaled to 200 %. Next to the graph a video is displayed with 50 fps scaled to ~50 %. Data are acquired via UDP for the U16-array and a USB3 camera (ImagingSource).

The second VI is for testing and very simple “test VI”:

A string indicator on the Front Panel (FP) and a FOR-loop (100 iterations) containing a first and a second property node of the string indicator (properties tested: visible off/on; text color red/green and value 0101/1010) alternatively a first and second local variable of the indicator with a constant as input (0101/1010) instead of the property node. The time for the execution of these two commands is measured for each iteration and the maximum is logged (stacked sequences: elapsed time in last sequence minus elapsed time in first sequence).

Test-Scenarios (iteration time measured with “test VI”):

1 UPD VI off test VI on: max. required loop iteration time ~2 ms for property node and ~0 ms for local variable

2 UPD VI on; streams off test VI on: max. required loop iteration time ~20 ms for property node and ~1 ms for local variable

3 UPD VI on; streams on test VI on; UPD FP minimized: max. required loop iteration time ~30 ms for property node and ~1 ms for local variable

4 UPD VI on; streams on test VI on; UPD FP maximized: max. required loop iteration time 12 seconds (typ. 2 – 4 sec) for property node and a few ms for local variable

5 UPD VI show intensity graph and hide video; FP maximized: max. required loop iteration time 12 seconds (typ. 2 – 4 sec) for property node and a few ms for local variable

6 UPD VI hide intensity graph and show video; FP maximized: max. required loop iteration time ~30 ms for property node and ~1 ms for local variable

Hide/show via property nodes at start-up

7 Run a build of UDP-VI: all variants of the test VI need a few ms

So, the problem exists if the first VI displays an intensity graph which is updated every 20 ms and the test VI uses a property node of an indicator and if both are running in the LabView environment.

At least I know now the root cause and have a work-around with the *.exe.

A second problem I saw was that the test VI is completely stalled if the UDP-stream for the first VI stops while the VI is running – but I think I can manage this.

I would appreciate if anyone has a suggestion how to solve the intensity graph / property node problem.

THX

Stephan