LV FPGA Compile Server Error

[czaum]

Hello!

Some time ago, I reported a FPGA compile server error with LV8.5 under Windows XP.
http://forums.ni.com/ni/board/message?board.id=280&message.id=3050&query.id=44591

The compiling stopped with following error message:

Mapping design into LUTs...
ERROR:MapLib:661 - LUT2 symbol
   "mytop/n_3491/n_3486/n_3475/n_3467/HiCompare/BU2/U0/gen_structure_logic.gen_n
   onpipelined.a_lt_ge_gt_le_b.i_gen_carry_chain_comp/sel_0_mux00001" (output
   signal=mytop/n_3491/n_3486/n_3475/n_3467/HiCompare/BU2/U0/gen_structure_logic
   .gen_nonpipelined.a_lt_ge_gt_le_b.i_gen_carry_chain_comp/sel<0> has input
   signal "mytop/n_3491/n_3486/n_3475/n_3467/HiCompare/b<15>" which will be
   trimmed. See the trim report for details about why the input signal will
   become undriven.

There was a reply to change the regional settings to "english" to solve the problem. This didn't worked.
I tried now to compile the VI with another computer with german Windows Vista Business Edition and the
same error occured.

Can anyone tell me which source may cause that error?

Kind regards,
Christopher Zaum

[Christian Mergl]

Hey,

I would suggest to follow with this topic at the other thread.

Christian