Notice that my compile reports show that 8 DSP48E blocks are being used. I guess it depends on the 'mood' of the Xilinx compiler. In your case your application is neither demanding nor fast so 'efficiency' is not an issue. Also interesting to see that you are now using BRAMs for your FIFO (16 out of 19 blocks)
On a different note (and just checking), you'll have to adjust your FXP operation formats. For example the top multiplier (in your original VI) takes <+/-, 32, 16> inputs which requires an output format of <+/-, 64, 32> if you want to avoid overflow and keep full resolution. It is generally ok to reduce resolution of your result but risky to reduce integer word length (especially when you choose wrapping like you do). In your case your output is set to <+/-, 30, 15> so you are cutting 17 MSBs out. It may be intentional but most likely you should either reduce the integer word length of your inputs or increase the integer word length of your output.
Consider using the 'free' Reinterpret Number function that acts as Scale By Power of 2 on your Fixed-point but without loosing resolution. It makes it easier to keep track of integer word length through your calculation chain.
