FPGA reference is lost upon stopping

[Socratesnote]

Hi all,

I'm having a problem with my MyRIO-1900, specifically with the FPGA functionalities. I have looked as far and wide as I can think, but have not yet found a solution to my problem (or even any post that concerns my problem.

So what is my problem you ask? In short: when I boot up LabVIEW, compile my FPGA-VI and run my Master-VI (on the RIO RT Target), it will work just fine. However, after I stop the Master-VI (using a soft-stop, not abort) the FPGA reference is lost and the only way to restore functionality is recompiling the FPGA-VI.

Long explanation now. I'm using a slightly modified version of the default FPGA personality, which is expanded to include 4 encoders on the A and C channels and do manual indexing of the encoders. Also I removed some excess code from the B-connector and Accelerometer/button, since I don't need those and the compiler began spouting errors about potential memory shortage (although the final placing was just fine). Anyway, those changes are probably not the cause of my error, since I can run the FPGA-VI in interactive mode just fine.

I'm also using a Master-VI to do a whole bunch of calculations and merge information from a large set of inputs. The problem is in the interaction between the two. It seems as though Open FPGA VI Reference only refers to the correct FPGA VI directly after compiling, but once the connection between the two is closed once, this reference is lost and communication fails. The error LabVIEW gives me is 'Error -63195 occurred at niLvFpga_Close_Dynamic.vi. Hex 0xFFFF0925 The handle for device communication is invalid or has been closed. Restart the application'.

Thing is, restarting is insufficient. Rebooting the RIO-1900 doesn't help. Closing and restarting the project doesn't work. Erasing the bitfile, re-downloading, restarting also doesn't help. As of now, the only thing that works for exactly 1 attempt is recompiling and running immediately after.

Other things I've tried:

-The problem is not in the VISA session being closed: I added the solution from http://digital.ni.com/public.nsf/allkb/CB82AC9CBC6C3F2386257241007A06EF but to no avail.

-I've tried this with one of the examples (customized FPGA Signal Generator). This one doesn't seem to have the problem, but copying the approach for opening and closing the FPGA didn't solve it.

-I've played around with the settings for automatically starting the FPGA-VI. Auto-run upon loading to the MyRIO, upon calling the reference, manually starting... all the same. 

-Both 'Close' and  'Close and reset if last call' from Close FPGA VI Reference have the same effect.

So, I'm at the end of my rope. I've included the FPGA and Master VI so you can see the part of opening the reference and closing it, but I'm not sure how much more MWA I can make it except for just opening and closing the FPGA VI reference. (Some of my code is not supposed to be shared with the outside world, so I can't post the whole batch).

I would greatly appreciate any help, pointers, tips, what have you.