Is there "rising edge"-block in labview?

[Jani]

And block down counter? rising edge comes from button, digital line etc..

[EdDickens]

Check out the free OpenG toolkit.

It has a 'Boolean Trigger' VI. I think this will do what you want.

Ed

[Salvador_Santolucito]

I'm going to need some clarification on your question... what exactly are you trying to do? Do you want to trigger an aquisition on the rising edge of you digital line? Do you want to monitor the digital line and use software to detect/count rising edges?

Please describe your application.

Thanks,
Sal

[Jani]

I want to detect rising edge on labview, digital line or when my program sets boolean block to true.
Like when i press the button.

[EdDickens]

Try the attached 'Boolean Trigger' VI. It can detect both a rising and falling edge of a boolean value.

The attached is saved in LabVIEW 6.1, but it upgrades with no problems to 7.0 and 7.1.

Ed

[asdsd33]

Hi

I want to detect rising edge of FPGA DIOs(trigger0 in attachment) to the RT side.if rising edge happen i have to send some data to FPGA. For this i took while loop on RT side and read boolean indicator(DIO trigeer 0) from FPGA to RT and inplimented some logic to detect rising edge(plz see in attachment). if this indicator(2v on DIO) is true i am executing true case shown in attachment(dont consider logic inside true case).My problem is on RT side true case(plz see in attached file) is executing for both rising and falling edge.As per the logic imlimented to detect rising true case should execute only for 0v to 2v change on pin but this true case is execute for 2v to 0 v change on DIO pin.Why this happen.Can any one  plz tell me.

I am testing this with power supply appalying 0v and 2v across the DIO pin no 86 of sbrio 9606.  

[GerdW]

Hi asdsd,

did you do some debugging using probes? What are the values on each wire before the AND function?

This is basic LabVEIW knowledge: did you go through all the free online LabVIEW beginner courses offered by NI?

And you still don't follow the advices given to you…

[asdsd33]

yes i did...As per the logic initially o/p will 0 bcz vtg across DIO is 0v.when i apply 2v to DIO pin it should b 1 rit?this is correct but after this when i apply 0v again it should be zero as per the logic but it is giving true(this is problem).for this also true case executing.i cheakd values before AND gate it is showing true for both i/p for this case.

I tnk there might be two resion for this

1) bcz of getting delay on RT side?

2) bcz of may be i am not giving vtg on pin properly?

i set power supply to 2v and using PS swich(ON/OFF) to apply trigger(rising edge).

Can u plz tell me wht is exat prob?

Thaks in advance.... 

[crossrulz]

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asdsd33 wrote:

i set power supply to 2v and using PS swich(ON/OFF) to apply trigger(rising edge).

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There's your problem.  Power supplies are known for having A LOT of capacitance on them.  So even though you turned off the output of the power supply, there is still a good amount of voltage there.  If you insist on using the power supply, I recommend at least one of the following options: 1) set the voltage of the supply to 0V to turn the digital line off or 2) add a resistor to ground to pull that voltage down (something around 1kOhm should work).

[RavensFan]

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@asdsd33 wrote:

yes i did...As per the logic initially o/p will 0 bcz vtg across DIO is 0v.when i apply 2v to DIO pin it should b 1 rit?this is correct but after this when i apply 0v again it should be zero as per the logic but it is giving true(this is problem).for this also true case executing.i cheakd values before AND gate it is showing true for both i/p for this case.

I tnk there might be two resion for this

1) bcz of getting delay on RT side?

2) bcz of may be i am not giving vtg on pin properly?

i set power supply to 2v and using PS swich(ON/OFF) to apply trigger(rising edge).

Can u plz tell me wht is exat prob?

Thaks in advance.... 

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