Hi
I have a cRIO 9075 & NI 9871 to develop a project so I looked for the example of "NI 987x-Serial Loopback" to study first.
However, there are some details I can't figure out clearly.
The following image is code from FPGA,
It seems it would update the "Byte to Write" and transmit by FPGA, and then send the interrupt to notify the Host.
The following is the write part of the code from the Host(RT).
It will update the Op Control to write case, and update the "Byte to Write".
My question is what happened if the Write Byte Node in the FPGA code timed out?
In this example, it sets the timeout of the "Write Byte" to 100ms, but if RT is slow, say 1 second, to send the "Byte to Write" to the FPGA, it should be timeout, but I don't know what's the consequence.
I found out the reference http://zone.ni.com/reference/en-XX/help/370984R-01/lvaddon11/crio-9870/
It mentions that if no data is available, it will keep retrying!!!
As a result, it will retry and retry until the "Byte to Write" being updated in the RT code?
I tried to make my question clear enough, if there's something confused to you in my description, please let me know, I would try my best to explain more.