How to synchronize FPGA with DaqMX counter pulse

[AntLee29]

Hi, our lab is currently using the PCI-7811R FPGA with the PCI-6221 Daq card.  The Daq card is outputting two analog signals which are triggered off the first rising edge of the internal counter as seen in the attached signals.vi.  This counter signal, which goes as fast as 65536 Hz, needs to run the FPGAwrite subvi on every rising edge of the pulse to send data to the FIFO.  I'm not sure how to implement this, and I have left it unwired in my signals.vi.  Could someone assist me with this?  Ignore the missing subvis, those are already working.  Thanks!

-Anthony

[AntLee29]

bump

[Verne_D]

If you want to implement triggering on the FPGA, you should do it in the FPGA vi, rather than the host. 65 MHz is pretty fast, so you'll need to make your change detection code run in a single cycle timed loop with a quicker derived clock. Have you programmed much in FPGA before?

[AntLee29]

I've programmed a bit of FPGA, but not to the point where I'd call myself an expert with it.  I understand everything going on in the attached FPGA vi and our primary FPGA vi (not attached).

I was hoping to implement it into the host because the desired frequency of the pulse from the daqmx counter has already been implemented in a much larger application, and it is actually a control on the front panel.  Changing the location of the source would require rewriting a lot of code.  65536 Hz will be the fastest possible frequency so I went ahead and wired the worst case scenario into the attached vi.  Also the desired frequency is approximately 65 kHz, not MHz.

I'd simply like to find a way to use the 65536 Hz pulse from /Dev1/Ctr0InternalOutput to run the FPGA subvi at every rising edge of the pulse if possible.

Thanks for your help!

[Verne_D]

Sorry about the misread, but even 65kHz will probably be too fast for your RT loop. The FPGA is capable of doing this onboard, but the architecture may not keep up if you implement it on RT. I'd output the counter output to a PFI and then monitor it in the FPGA VI.