How to optimize this labview fpga vi??

[mangood]

---

@nathand wrote:

No, because the loop timer is a timer, not a wait function. It waits until 1000ms have elapsed since the previous time it ran. It does not wait 1000ms every time. If it takes 900ms to read and write the IO and do the calculation, the loop timer will wait only 100ms in order to maintain the 1hz loop rate. The only time this does not work is if the IO and calculations take more than 1000ms, in which case the loop timer has no effect.

---

Yes yes yes

I  read about timer in labview but I got nothing

But your explain amazing 
I am now

take this from me and to all good people in this world

best regards

m.s

[mangood]

---

@nathand wrote:

No, because the loop timer is a timer, not a wait function. It waits until 1000ms have elapsed since the previous time it ran. It does not wait 1000ms every time. If it takes 900ms to read and write the IO and do the calculation, the loop timer will wait only 100ms in order to maintain the 1hz loop rate. The only time this does not work is if the IO and calculations take more than 1000ms, in which case the loop timer has no effect.

---

dear:
u said if code take longer than 1000ms the loop timer has no effect.

during read some toturial i note this as below in rectangle red

-------------------------------

I am confident  you reply,But this figure made me confused

because as i understand from it that the loop """adjust it value to total code execution time"""

or is  their wrong in my understanding

regards

[nathand]

The loop timer help may make it clearer:

"If an execution instance is missed, such as when the logic in the loop takes longer to execute than the specified interval, the Loop Timer Express VI returns immediately and establishes a new reference time stamp for subsequent calls."

When the logic takes longer than the loop period, the timer does nothing - it doesn't wait at all. The loop timer always waits since the last time it was called; it doesn't know the history. If one iteration takes too long, it will not subtract that time from the length of time to wait the next time. The time between iterations will never be less than the timer value - it will not catch up by shortening an iteration when the previous one runs too long.

[mangood]

ok

best regards

[mangood]

Hi

during work today I find that this file """nilvfpga_acknowledger_Spartan 32"""" is missed from  support files that AVAILABLE for spartan 3e

DOSE ANYONE HAVE IT!???!! please

regards

[nathand]

Can't help you there, unfortunately. You might start a new thread, since it is no longer on the topic of optimizing an FPGA VI. You may get more helpful responses in a new thread where the subject matches the question.

[mangood]

yes i think i must did what you say

[mangood]

Dear ::

after previous discussion about how to optimize some my lv vi

the vi was optimizes

but toady I Fell in big trouble..

which it as in figure

i was build an array of boolean but the labview fpga say error:

labview fpga suggest  to me do the following:

Arrays must be a fixed size in the current target. Use the following suggestions to help troubleshoot the problem.

1. An array control, constant, or static indicator is not a fixed size. From the front panel window, right-click the control, constant or indicator and select Set Dimension Size from the shortcut menu. Verify the size is fixed.

2.  The source of an array wire or indicator is not a fixed size. Locate the source and from the front panel window, right-click the source object. Select Set Dimension Size from the shortcut menu and verify the size is fixed.

3.  An array wire or indicator comes from an array function, such as the Build Array, Cluster To Array, and Initialize Array functions, and the VI is not configured for autopreallocation. Open the VI Properties dialog box, select Execution from the Category pull-down menu and verify that the Autopreallocate arrays and strings checkbox contains a checkmark.

4.  An array wire or indicator comes from an array operation and LabVIEW cannot determine the static size.  Refer to the LabVIEW Help topic, "Returning Fixed-Size Arrays from Array Functions", for information about wiring array functions in FPGA VIs.

i canot get anything to solve

any help please

bet regards

[mangood]

hi

the problem was solved

from here http://forums.ni.com/t5/LabVIEW/Build-Array-in-FPGA-module-SOMETIMES-gives-error-quot-Arrays/td-p/60...

the step is

When you open a non FPGA VI on an FPGA target, and when the VI is using arrays, you will have to do the following steps
File> VI Properties > Catergory= Execution : Check the "Autopreallocate arrays and strings".

However, when you copy the code into a new FPGA VI, this property is checked by default and so the VI is not broken!
On a non FPGA VI, this property does not exist (as it is not required).

[mangood]

 dear :

I have something I want to discuss and related to optimization
and also is  related to explain the work of labview fpga compilation

as you can see from figure below its explain to FPGA implementation of not gate

you can see their is a FF(here one bit) between each element

so the maximum path delay is determind only by Max delay element which here ex .Not gate

so its mean that always the system in labview fpga  except single loop cycle is pipelined

And so why we use feeback loop to make pipelined if we have already a reg between element???