Compilation error in importing VHDL Wrapper file for Verilog code into LabVIEW FPGA via CLIP node method on SbRIO9606 and SbRIO 9642 platforms respectively

[aijaz]

Hi,

I posted same question on http://forums.ni.com/t5/LabVIEW/How-to-import-Verilog-codes-into-LabVIEW-FPGA/m-p/2223000/highlight/... but on advice given to me on this link, i have started this new thread (instead of expecting urgent help on that already solved thread).

Now coming to the issue;i am facing problem in successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:

1. I am working on platform SbRIO-9606.
2. Labiew version used is 2011 with Xilinx 12.4 compiler tools
3. NI RIO 4.0 is installed
4. Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code for SbRIO 9642 platform, but problem remains same for both versions and for both boards)

Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?

1. Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd

///////////////// Verilog code of “simple_and.v”//////////////////////

////////////////////////////////////////////

module simple_and(in1, in2, out1);

   input in1,in2;

   output reg out1;

   always@( in1 or in2)

   begin

      out1 <= in1 & in2;

   end

endmodule

////////////////////////////////////////////

/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY SimpleAnd_Wrapper IS

    port (

        in1    : in std_logic;

        in2    : in std_logic;

        out1   : out std_logic

      );

END SimpleAnd_Wrapper;

ARCHITECTURE RTL of SimpleAnd_Wrapper IS

component simple_and

   port(

         in1    : in std_logic;

         in2    : in std_logic;

         out1   : out std_logic

      );

end component;

BEGIN

simple_and_instant: simple_and

   port map(

            in1 => in1,

            in2 => in2,

            out1 => out1

            );

END RTL;

////////////////////////////////////////////////

Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:

1. NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3

• In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.

Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.

Query3. The post-translate model file can  also be generated by implementing verilog simple_and.v  file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?

2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.

• In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.

Query4. What is the difference between this method and the above one?

2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.

Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file

1. Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.

WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.

2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.

3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.

Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!

4. ERROR:MapLib:978 - LUT6 symbol  "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details.  Output files will not be written.

Seeing these errors I have reached the following conclusions.

1. There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.

Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?

2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.  

3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.

P.S.

I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml,  Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.

Please note that I have made all settings regarding:

• Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
• Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
• Synchronization registers are also set to zero by default of all CLIP I/O terminals.

Please I need speedy help.Thanking in you in anticipation.

[alcava.cr]

Hi there, is recommended to use the version of Xilinx ISE that installs along with LabVIEW FPGA Module. Plus the article that you mention says "...DO NOT use the latest versions (11.1 or later)". I would go back to an older version and try another compilation.

[aijaz]

First of all, thankyou for replying to my question. As far as that suggestion for not using xilinx version 11.1 or later is concerned in that article, it is with reference to labview fpga 2009; as can be verified in the question statement. In labview 2011, xilinx 12.4 xompiler tools are installed. I have tried using xilinx ise 10.1 version (in pc) for generating .ngc file for sbrio-9642; but it gives same errors and warnings. Since sbrio-9642 has spartan3-xc3s2000 mounted on it, so i could try it with ise 10.1 version in pc. But for sbrio-9606, i had to use a xilinx ise version for generating required .ngc file,in which spartan6(xc6slx45) could be selected. So i installed xilinx ise 12.4 webpack in pc and tried compiling but the same errors.
May be the issue is that after post translation step in xilinx ise, i do not get a simple_and_translate.vhd file, instead its a simple_and_translate.v generated. And in final labview compilation, it takes that simple_and componentin vhdl wrapper file as blackbox and therefore could not recognize. Maybe i am missing some sort of compile library settings or include library directory settings while generating simple_and.ngc file. Somehow that verilog component could not be binded to wrapper vhdl file.
Whatever is causing this issue, it has to be something very basic. Bt its troubling me now, because its quite a time i m stuck on this step. ..

[alcava.cr]

you are welcome! I comment this problem to a more knowledgeable co-worker and here are couple things that you can try:

1. Regardnig: ERROR:MapLib:979 - LUT6 symbol during mapping stage. A similar issue was resolved by changing the VHDL wrapper declaration all to UPPER CASE.

2. The fact that the IP Integration Node can not generate the IP might be an indicator that the code needs adjustments. So, check if your code is good.

3. Consider posting & searching at the Xilinx forums as well. For example, take a look at this discussion. Perhaps someone have seen this before and can give you an answer regarding the VHDL code.

Another helpful resource » http://www.xilinx.com/support/answers/40379.htm

[aijaz · Accepted solution]

Thankyou for your suggestions and time; i did try changing VHDL declaration to Upper-case but it did not work. Those Xilinx links were helpful to some extent but they were more related to problems occurring in a projects implemented in Xilin ISE. However, before posting to Xilinx forum, my problem luckily got resolved!

Actually the key was that; XML utility of Labview 2011 when generates .xml file, it does not include names of verilog modules and sub-modules in its "Implementation list". That's why Labview compiler always considered "verilog instant" in VHDL Wrapper as a Black-box, and consequently translation and mapping failed.

Therefore i manually added Implementation list in XML file according to my hierarchy of Verilog files in Xilinx ISE. This simple step resolved the problem on which i had been stuck for long. But please tell me some other solution of this problem aswell, as XML utility of Labview 2011 should automatically include verilog files in Implentation List rather to add them manually. Labview 2009 automatically adds verilog instantiated files under "Implementation List" so why not Labview 2011 XML Utility does the same?

Anyways, thanks for your consideration regarding this issue. Waiting for some alternative solution as well, if any.

Cheers!

Anum Ijaz