@XM43 wrote:
Hi,
I have an FPGA VI that reads various style quadrature encoders and calculating their various parameters which leads me to a total of 64 (15 controls and 49 indicators). I do not wish have so many controls and indicator on FPGA for efficiency and aesthetic reasons. Post testing, I am thinking of building an array of similar data types and translate boolean to numbers and then send to RT using a FIFO.
But I am wondering if this would make a difference in efficiency or will it be the same? Also, the subject of post, am I hurting FPGA with this many FP objects. I vaguely remember reading that the Read/Control Method on RT side with too many items, consumes a lot of RT resources.
There are some additional issues which may or may not be of interest:
AFAIK, the actual implementation of reading / writing the registers instantiated for the FP controls (internally, we don't actually see these directly) are in the default board clock domain. Reading or writing the FP controls in another clock domain will incur some buffering, typically 2-3 times the bit width and leads to the "registers" actually being implemented as "handshake" items instead.
Not a lot we can do to change this, but the resource cost of the FP controls can end up being higher than expected from the raw register count. It can end up being more efficient to group smaller controls into clusters to reduce the handshake overhead. 32x individual Booleans with clock domain crossing cost more fabric (~150) than a single 32-bit number (~36) due to the 4-wire handshake registers required for the clock domain crossing.
