How fast is the Wait On Rising Edge function on FPGA?

[otheredward]

Hello,

I'm trying to get up to speed on FPGA labview before I buy a card. I see there is a Wait on Rising Edge method which waits until a rising edge has been detected on the specified DIO line. If you use this function with the R Series boards, which all appear to be clocked at 40MHz, can anyone tell me the time resolution with which the rising edge is detected? That is, if the DIO line goes from low to high with a rise time of 5ns is that noticed immediately or is there a couple clock tics before execution proceeds?

Thanks.

[Larry_H]

Edward,

The time it takes for the FPGA code to recognize the DIO line going high can range from immediately to 25ns. Since the clock is set to 40MHz, it can only recognize the change as fast as the clock is set to run. However, although that is the base clock speed, you are not limited to a 40MHz clock. You can use a derived clock rate, as explained here, to get a faster clock speed and thus reduce the amount of time it would take for your code to recognize the rising edge.

Regards,

Larry H.

[otheredward]

Hi Larry,

Thanks for the info. I have seen the FPGA derived clock and wondered about this. I talked with a couple people on the phone at NI who told me that the DIO lines are only rated to 40MHz and anything beyond that isn't guaranteed. Can the DIO lines be polled at speeds well above the 40MHz clock speed? Any idea what the upper limit is? (We have some colleagues who also use FPGA and run a single cycle timed loop at 80MHz on the 7830R board and seem to think it works fine.) When I called NI I also asked if the 40MHz clock is the board clock and does the FPGA have its own, separate clock? I didn't get a clear answer on this, any insight?

Thanks very much,

Edward

[Larry_H]

Edward,

Your information is correct in that the DIO lines are only rated to 40MHz and anything beyond that isn't guaranteed. With that said, it is very possible to use the DIO lines at faster speeds, as your colleagues have demonstrated, but again, we can't guarantee that will work. In regards to what the upper limit may be, we do not have that information spec'd because of the 40MHz rating. The limitation of our speed is completely due to the 40 MHz that oscillator that we use.

In regards to your question about the on board clock and the FPGA clock, the FPGA does not have its own separate clock. The FPGA simly uses the speed as determined by the oscillator it is connected to which, in our R series board cases, is 40MHz. I hope this provides you with the answers you were seeking.

Regards,

Larry H.

[otheredward]

Hi Larry,

I was looking at the data sheet for the R series FPGAs today and noticed the "Minimum Sampling Period" under the "Digital I/O" section is listed as 5ns (corresponding to 200MHz). I called NI and asked specifically what this spec meant. The first person I talked to had no idea, the second person told me he thought that corresponded to the maximum rate you could poll the DIO lines. Then he went and talked to another guy and confirmed this was correct. This appears to contradict the information I've gotten from NI the last two times I've called and previous posts here. Is the data sheet incorrect or does "Minimum Sampling Period" mean something else and the guy I just talked to at NI was in error? If "Minimum Sampling Period" means something else what does it mean?

Thanks,

Edward

[Larry_H]

Edward,

The information you were given is correct and is actually additional information in regards to your original question to me. I'm assuming the information you are referring to is this:

Minimum pulse width
Input		25 ns
Output		12.5 ns
Minimum sampling period		5 ns

I spoke with our product experts who interface more frequently with R&D, along with the engineer that you spoke to, and confirmed the following information in regards to the numbers above:

The minimum input pulse width of 25ns, or maximum input frequency of 40 MHz, corresponds to the speed of the input digital signal. So according to our specification, we can guarantee that you can feed a 40 MHz digital signal into your R Series card and it will catch every pulse. The minimum sampling period of 5 ns, or maximum sampling frequency of 200 MHz, corresponds to the rate at which we can poll the input signal. So by these numbers we guarantee that you can poll a 40 MHz digital signal at 200MHz and capture your input pulses. Naturally, as we've discussed in previous posts, you can feed a faster digital signal into your card, however NI does not guarantee performance at input speeds above 40MHz. I hope this clarifies the answers to your questions. If not, please feel free to let me know.

Regards,

Larry H.

[otheredward]

Hi Larry,

Thanks very much for the clairification. That appears to be a very subtle but very important distinction you've made. Thanks very much for checking this out, this totally clears up my question and I'm definelty going to order a board now. Seriously apperciated.

Best,

Edward

[Larry_H]

Edward,

I'm happy to hear that I was able to clear all confusion for you so that you feel more confident in your purchase. If you run into any problems in the future with using your card, please feel free to call NI and me, along with the team I work with, will be more than happy to help out. I hope you have a wonderful rest of the week.

Regards,

Larry H.