How can I use LabView to control Altera Scripting

[JohnM67]

Hi

I have kind of run into a stone wall. I am building a production test executive based on LabView. Part of this process includes loading an FPGA image on to a CFI flash that is in the JTAG chain. I am trying to make so that the production operators don't have to open a second application, select the right FPGA and Flash navigate to the file then load it, then go back to LabView and run the rest of the tests.

Altera has a command line interface that will let me load .cdf file.  The problem is that nowhere in Altera’s documentation does it show me how to first load the “Parallel Flash Loader IP” into the FPGA. The flash loader acts as a temporary bridge between the JTAG input and the CFI Flash.  I have looked on Altera’s Forums and have had an open ticket with Altera’s support engineers for more than a week.

I can’t be the first person to want to do this; I am hoping someone here has done it before. I would really rather not try to use the activeX controls to manipulate the windows based program.

Any suggestions would be greatly appreciated (Note I am not trying to put LV code on the FPGA/Flash just use LV to control the process)  

Thanks in advance

Below is the error message and the script I am using. It almost works just missing the flash loader IP

C:\altera\12.1sp1\qprogrammer\bin>quartus_pgm -c USB-BLASTER -m JTAG  S_FPGA.

cdf

Info: *******************************************************************

Info: Running Quartus II 32-bit Programmer

    Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Full Version

    Info: Copyright (C) 1991-2012 Altera Corporation. All rights reserved.

    Info: Your use of Altera Corporation's design tools, logic functions

    Info: and other software and tools, and its AMPP partner logic

    Info: functions, and any output files from any of the foregoing

    Info: (including device programming or simulation files), and any

    Info: associated documentation or information are expressly subject

    Info: to the terms and conditions of the Altera Program License

    Info: Subscription Agreement, Altera MegaCore Function License

    Info: Agreement, or other applicable license agreement, including,

    Info: without limitation, that your use is for the sole purpose of

    Info: programming logic devices manufactured by Altera and sold by

    Info: Altera or its authorized distributors.  Please refer to the

    Info: applicable agreement for further details.

    Info: Processing started: Thu Oct 03 18:16:53 2013

Info: Command: quartus_pgm -c USB-BLASTER -m JTAG S_FPGA.cdf

Info (213045): Using programming cable "USB-Blaster [USB-0]"

Info (209060): Started Programmer operation at Thu Oct 03 18:17:19 2013

Error (209062): Flash Loader IP not loaded on device 1

Error (209053): Unexpected error in JTAG server -- error code 5

Error (209012): Operation failed

Info (209061): Ended Programmer operation at Thu Oct 03 18:17:21 2013

Error: Quartus II 32-bit Programmer was unsuccessful. 3 errors, 0 warnings

    Error: Peak virtual memory: 376 megabytes

    Error: Processing ended: Thu Oct 03 18:17:21 2013

    Error: Elapsed time: 00:00:28

    Error: Total CPU time (on all processors): 00:00:03

[Erik-S]

Hello John,

What is the interface that you are using to send the information via LabVIEW (i.e. VISA)? Have you also tried using the System Exec VI in LabVIEW to access the command window? Here is a KB that shows how this is done:

http://digital.ni.com/public.nsf/allkb/8E19CA81874FFDD786256BE40066C151

Also, feel free to post your LabVIEW code as that will help us to get a better idea of what is going on.

-Erik S.

[JohnM67 · Accepted solution]

Hi Eric,

I got it figured out today, basically you have to load the Parallel Flash Loader first into FPGA ram. It is a special .sof file (pfl_epXXXX.sof) based on your FPGA. Code is actually pretty straight forward, using the Sys Exec VI. Use the windows based programmer to generate the .cdf file that identifies your FPGA, attached Flash and .pof file .

Syntax was odd going into Sys Exec. Note the extra "C" in in front of the "quartus_prm.exe" I have no idea why that was needed, but I was getting an error until I just happened to put it in there (Blind Luck :-))

I used a 2 element array going into a four loop

cmd /cquartus_pgm.exe -c USB-BLASTER -m JTAG -o P;pfl_epXXXX.sof

cmd /cquartus_pgm.exe -c USB-BLASTER -m JTAG S_FPGA.cdf

Defining the working director C:\altera\12.1sp1\qprogrammer\bin

And added match string with "Successfully performed operation" on the output in the loop to make sure everything loaded correctly then adding the array to give me a overall P/F

To anyone doing this same thing Altera's documentation is poor to say the least. It took most of a week to figure this out Not allowed to upload code, so anyone wanting details just post here and I will try to help. This was painful, with lots of lessons learned.

Thanks for the interest though

Best regards John

[buton]

This was helpfull since i am trying to do the same...it worked

[Suppy]

Hi

I want to communicate altera cyclone FPGA with labview. can any one provide me the steps to do so. I have already tried to follow the steps written here. But not yet got any success

[JohnM67]

Hi

A couple of things that may help, first the full Altera package needs to be installed on the client (Freeware version works). Second test your ".cdf" file. That has to be done from the Altera windows based S/W. Also can you post your syntax and error messages?

John

[Suppy]

I have already installed quartus 2 software. where do i need to install this altera package? Actually I am not getting any connection with the labview. Even I am not getting response. Wher can I found this .cdf file. In bin folder its not. So please send me the link from where i can cownload this file.

[JohnM67]

I just reread you message. 

You are calling the altrea shell from LabView, you have to point sys exc where the altrea s/w is and where your files are. The Chain description file is is created from Quartis programming tool    

[Suppy]

Thanks a lot for your help. I have progressed a bit. The problem I am facing now is due to the mode. Basically I am using Passive serial mode for configuring the FPGA. It is showing this mode is illegal. Furthermore I am trying to load .sof file but still it is showing error.

Thanks once again for your help.

[JohnM67]

I would suggest trying to manually type in the syntax from the shell without LabView. That should tell you if it an Altera issue or LabView