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How array is handled from Host using DMA FIFO (Host to Target)

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Hi folks,

 

I'm trying to pass an array of setpoints from the Host to FPGA using DMA FIFO. Let's say the array contains 20000 elements. My FIFO on the Host side can only contain 16000 or so elements. Will the data be written element-by-element regardless of the array size or do I have to partition the array into smaller arrays before the FIFO Write method? Let's say I write to the FIFO with smaller, 1000-element arrays. The FIFO will read 1 element at a time from the FPGA side so will the data flow be blocked until I clear at least 1000 free elements on the FIFO Write method, at which point it writes all 1000 of the next setpoints at once? Or will the setpoints be written continuously as soon as individual elements are cleared from the number of elements available to write?

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I don't know the answer to this question, but you could test it out pretty quickly, probably without even compiling an FPGA target (by running it in simulation). Configure the FIFO for some small number of elements, write an array larger than that, see if it returns with a timeout error.

 

However, why not just increase the size of the FIFO on the host side? The help recommends that the host-side buffer be configured for 5 times the number of elements that you want to read or write.

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Accepted by topic author Uxorious

Hi Nathan,

 

Sorry for the late update but I just thought I should follow up. I took your advice and just tested it out for myself (I probably should have done this before posting). Turns out that the array data will write even if there are not enough empty elements to contain the entire array. However, it will still block until enough elements are read and cleared from memory on the FPGA side to pass the entire array. So if it is data that is constantly being read, it is still better to pass the data through as smaller arrays if you don't want to increase the amount of memory the Host FIFO occupies on your system. However, if you can afford the memory then as you've mentioned, you can always increase the depth of the Host-side FIFO. From what I understand though, attempting to write larger arrays to a Host to Target FIFO buffer does not decrease overhead (as is the case with a Target to Host FIFO) since it still passes one element at a time to the FPGA-side FIFO regardless.

 

Thanks again for your help.

 

Regards,

 

John A

 

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