I've hit into a bit of an issue when trying to utilise an FPGA + I/O module setup for high speed communication with a device via a mix of LVDS and SE pins. I'm trying to run at a variable clock anywhere between 210 and 40Mhz and when running initial tests I've encountered two problems:
- When running using a derived clock rather than a base Labview will not let you read and write from a bank of pins at the same time, I've been in contact with support and this is a known issue, as such will need a different approach
- Strange compilation issues wherein the reported timing errors do not match the underlying Vivado reports, for example when the initial timing is generated the clock is ~10Mhz below the target (which is the usual as it is highly pessimistic) and after the actual timing report this has decimated itself down, leading to a result anywhere from 10 to 150Mhz below the target
We're now looking into using an external clock and finding a way of bypassing the timing restrictions on the I/O module, has anybody had any experience with this type of issue before?
We're running Labview 2015 SP1 with a 7953R FPGA attached to a 6583 I/O adaptor in a PXIe chassis, with the I/O module in DDR mode to allow for running at over 200Mhz.
Thanks in advance,
Are you using Xilinx IP in your compilations?
It might be worth posting on the Xilinx forums too if your seeing disparities in the Vivado Reports. A better idea of what the project you're wishing to compile will also be pretty helpful in trying to find a root cause of the issues you're facing here.
Technical Support Engineer