High resolution PWM in FPGA

[sodupuc]

Dear All,

I would like to know if it is possible to design a high resolution PWM in LabView FPGA, with a resolution better than nano second. I need to run the PWM output at 300 kHz with a high PWM resolution in ps or 0.01 % duty cycle increments. With current clock of 40 MHz, I get approx. 0.7% duty cycle resolution at 300 kHz.

I found this document on Internet that describes the principle in LV: http://ijarece.org/wp-content/uploads/2013/08/IJARECE-VOL-2-ISSUE-5-563-567.pdf

some more doc: http://gse.ufsc.br/~bezerra/students/PauloRicardoCecheleroVilla/papers/Modulador%20FPGA.pdf and http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05636571

Has anyone tried to implement this? How to configure the outputs?

BR, Uros 

[Hooovahh]

I truly hope you don't have those requirements.  Lets do some math.

Lets say you want to generate a PWM at 300Khz, and you want the duty cycle to have increments of 0.01%.  That means for a duty cycle of 0.01% you need to be high for about 3*10^-10 seconds (300000*0.0001=3*10^-10) and low for 0.000003333 seconds (300000*0.9999=0.000003333).  To get this resolution you need to be able to update your digital output at a rate of 3,000Mhz, or 3Ghz (1/3*10^-10=3GHz).

So no I believe you won't be able to do this with an NI FPGA.  NI does have some dititizers that are that fast but I have no idea what kind of control you have because I've never used one.

[sodupuc]

Thank you for your fast reply Hooovahh.

You are right, I came to the same conclusions regarding the clock needed for HRPWM. However, it seems that there are other possibilities on how to achieve this without enormous clock rate of the output pins. For example, TI has an MCU (C2000 series) with a resolution of 150 ps (http://www.ti.com.cn/cn/lit/ug/spru924f/spru924f.pdf) – basically they are using the same principle described in the papers without high clock rate.

The point is not in updating the digital outputs at such a high rate, but in precisely controlling the time between rise and fall of the digital outputs by implementing a delay line - using a delay-locked loop (DLL) - DLL can be used to change the phase of a clock signal, usually to enhance the clock rise-to-data output valid timing characteristics of integrated circuits.

Therefore, I would like to know if ti is possible to implement such a solution in LV FPGA? 

[GerdW]

Hi sodupuc,

that MCU will have some specialized hardware circuit implemented to realize the HR-PWM…

In the FPGA you will need to count clock pulses to realize your delay and so you're still limited to pulses of the used clock signal.

Usually the FPGA uses the 40MHz clock but you can generate additional clocks of atleast 80MHz. See for yourself how far you get…

[sodupuc]

Tnx GerdW!

Yes, I agree with you, the TI MCU is just an example of such a solution without using a high clock rate in the MCU.

However, in the papers from the first post they used the same master clock in the FPGA, i.e. 40 MHz. They achieved this using the delay-locked loop which is already present in almost all XILINX FPGAs used by NI. Here is an explanation by Xilinx: http://www.xilinx.com/support/documentation/application_notes/xapp132.pdf

The problem is, that there is no VI in the LV FPGA that exposes this functionality - phase delay of the master clock. Is there any way to achieve this functionality? Maybe by using FPGA IP integration node?