HDL node not picking up push button signals

[NapDynamite]

Hello,

I am trying to design a vending machine using sbRIO and Labview HDL node. But my HDL node doesn't seem to pick signals from push button (latched when released). I have successfully done the same thing using labview blocks but not geting desired results by HDL node. I could use labview blocks only and not HDL node but I have to give a presentation to my class about how we can integrate VHDL code in labview. I have attached my VI with following VHDL code living inside HDL node. 

process( clk, reset )
begin
if( reset = '1' ) then
state_reg <= idle;
enable_out <= '0';
elsif rising_edge(clk) then
state_reg <= state_next; -- result and enable_out follow input by 1 clock cycle
if( enable_clr = '1' ) then
enable_out <= '0';
elsif( enable_in = '1' ) then
enable_out <= '1';
end if;
end if;
end process;

process(state_reg,Five,Ten)
begin
case state_reg is
when idle=>
if (Five="0"and Ten="0") then
state_next<=idle;
elsif (Five="1" and Ten="0") then
state_next<=statefive;
elsif (Five="0" and Ten="1") then
state_next<=stateten;
elsif (Five="1" and Ten="1") then
state_next<=statedone;
end if;

when statefive=>
if (Five="0" and Ten="0") then
state_next<=statefive;
elsif (Five="0" and Ten="1") then
state_next<=statedone;
elsif (Five="1" and Ten="0") then
state_next<=stateten;
elsif (Five="1" and Ten="1") then
state_next<=statedone;
end if;

when stateten=>
if (Five="0" and Ten="0") then
state_next<=stateten;
elsif (Five="0" and Ten="1") then
state_next<=statedone;
elsif (Five="1" and Ten="0") then
state_next<=statedone;
elsif (Five="1" and Ten="1") then
state_next<=statedone;
end if;

when statedone=>
state_next<=idle;
end case;
end process;

process (state_reg)
begin
Ten_Deposited<="0";
Five_Deposited<="0";
case state_reg is
when idle=>
Ten_Deposited<="0";
Five_Deposited<="0";
done<="0";
when statefive=>
Five_Deposited<="1";
when stateten=>
Ten_Deposited<="1";
Done<="0";
when statedone=>
Ten_Deposited<="1";
Five_Deposited<="1";
done<="1";
end case;
end process;

[REDS]

Hello NapDynamite,

From your other post we were able to make it work but using combinatory logic (no clock signal in VHDL code). Since we don’t directly support VHDL, there is not much we can help you. If there is any VHDL guru here that can check your code, it would be great.

[NapDynamite]

And I did it! 

[REDS]

Awesome! I'm glad to hear that. Would you mind posting your code and some relevant notes? This will be very useful for the next person who faces these difficulties. Yey productivity!

[NapDynamite]

Sure 🙂

Here you go

[REDS]

Thanks, NapDynamite. However, you just included your Project (not the actual VI) on the attachment. A good way to include all of the dependencies is to create a source distribution (LLB). 

1. Right-click on Build Specifications, select New»Source Distribution
2. Under Distribution Settings, select Custom as your Packaging Option
3. Check the Destination is LLB box and click OK on the warning.
4. Choose the Destination Path where you would like the LLB to be saved
5. Click Build to create the LLB, or click OK to save the Build Specifications.

[NapDynamite]

Here you go. 

[NapDynamite]

Dear REDS,

I'm facing this terrible issue of posting any question to any discussion board over here. When I hit the POST button i get an error as shown below. 

I mailed to NI but haven't got any reply yet. I just could not find any other way to share this issue. I need help

[REDS]

Hello NapDynamite,

That is a strange behavior I haven’t seen before. Have you tried logging in, logging out and logging back in again? Maybe also try using another web browser, like Internet Explorer or Firefox.

I will ping the department in charge of this on our end so that they can help you.

[NapDynamite]

I tried everything but nothing seems to work. I have also mailed NI but no response from there. It has been a week now and I'm unable to ask questions which I've got in bulk. Your help will be much, much appreciated.

Regards.