HDL Node - How to import existing VHDL code

[jayde]

Hi,

I just starting using LabVIEW and LabVIEW FPGA.  My goal is to re-use some of the existing VHDL code that I have already simualated outside of the LabVIEW environment.

I wrote a simple VHDL program within the HDL-Node and got that working.  But I'm having trouble when I try to reference an external file.  Are there any special tricks involved? I was able to browse to the file and include it, but the HDL node never changed to indicate that it accepted the external code.  The syntax check passed.  But the I/Os on the HDL-Node never updated.  Is there some other step involved?

Also, would one have to edit a standard VHDL file to get meet the HDL node requirements?

Thanks for any suggestions/pointers.

Jayde

[Bassett_Hound]

Hi Jadye,

If you haven't seen these already, you can find a few pointers from the following links:

HDL Interface Node FAQ

Importing HDL Code into FPGA VIs using the HDL Interface Node

Integrating IP Cores into LabVIEW FPGA with the HDL Interface Node

If you have questions after this please let me know.

Regards,

Bassett

Message Edited by Bassett Hound on 06-18-2007 11:11 AM

[jayde]

Bassett,

Thanks for the info.  I have read these notes, but am still uncertain of the protocol.

Must the target VHDL code always be declared as a component in the code section? 

And must the user always type the top-module I/Os one at a time into the parameter section?

It's kind of difficult to type into those small windows of the HDL-Node Interface and I noticed that the Windows cut/paste shortcuts don't typically work.

Dorothy

[Coal_Man]

jayde,

The architecture for the hdl node must be either typed or copied into the HDL node window.  Along with that, the parameters will need to be manually input under the parameter tab.  Also, what file were you including for the external code.  You would include a compiled netlist or library in order to call it from your architecture.  The inputs and outputs will not change when you add an included file, only when you add an I/O parameter.  If you have any other questions, please let us know.

[jayde]

Hi Brian,

thanks for the pointers.  I'm still a bit confused.  The Application Note (Importing HDL Code into FPGA VIs Using the HDL Interface Node) seems to indicate that you can reference external VHDL code:  "...However, you also might want to include external HDL code...." 

I got the impression that one could reference either a netlist or a VHDL file in the "external files tab".  Including VHDL source in my case would be a lot easier because I wouldn't have to run it through the Xilinx software prior to including it in my LabVIEW design directory. 

If importing the VHDL source is not possible, I'll just cut and paste it into the HDL Node implementation window.

Jayde.

[Coal_Man]

Jayde,

Sorry if my last post was not clear.  You will need to copy and paste the VHDL source that you want to be compiled for the FPGA into the HDL node implementation window.

[Coal_Man]

Jayde,

Allow me to clarify further.  If you include your VHDL file as an external file, you will still need to define and instantiate the component in the implementation window and reference the included VHDL file if the component implementation is located there.  So no matter what, you will need to put code into the implementation window.  If you simply want to include the VHDL file that you have written, it is easiest to simply copy and paste the code.

[jayde]

Thanks for your help and suggestions. 

I did get the HDL node working.  The easiest way wound up being to attach my original VHDL code via the external file link and then instantiate it as a component.

There are a few quirks:

std_logic as defined in the port statement, winds up as std_logic_vector(0 downto 0) when transferred to the code segement.  There's no way to edit anything so I had to work around this by rewriting some of the code.

std_logic_vectors are "bit mirrored" as they enter the HDL node.  I worked around this by adding the LabVIEW "reverse array" block before sending signals into the HDL node.

It seems as if the HDL node is overly difficult to work with, almost as if the user is being deliberately discouraged from working with VHDL.  Hopefully this will be corrected in future releases.  Sometimes it just make sense to port and share already proven modules (one of the reasons that VHDL is so popular).

Jayde

[Emmanuelol]

Hi i am still confused in all this, i'm new in this FPGA module, i have a lot of VHDL code for that reason i want use the HDL node interface, but i don´t understand how use external VHD files, for example i tried to use a code for ps2 of keyboard this code shows the binary code ASCII from every key when you press the code is the next:

 library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity RegisterS_P is                        
    generic( n: integer := 33);
    port(
                     RST:in std_logic;
                     CLK_T:in std_logic;
          R:in std_logic;
          Q:out std_logic_vector(8 downto 1)
        );
end RegisterS_P;

architecture simple of RegisterS_P is  
signal Qn,Qp:std_logic_vector(n-1 downto 0);
begin                                           
    combinational: process(Qp,R)
    begin
        Qn(n-1)<=R;
        for i in n-2 downto 0 loop
            Qn(i)<=Qp(i+1);
        end loop;
        Q<=Qp(8 downto 1);
    end process combinational;
    
    sequenctial: process(RST,CLK_T)
    begin
        if(RST='1')then
            Qp<=(others=>'0');
        elsif(CLK_T'event and CLK_T='0')then
            Qp<=Qn;
        end if;
    end process sequential;
        
end simple;

someone can help me in how the use the HDL node to implent that code, also i read all example and information for this node, but i still so confused, well thanks 

[mishkin]

Have you looked at the above links? Those should at least get you started on importing your HDL code into Labview.

Which specific part are you confused about?