Getting Error -52000?

[MightyEKA]

Hello!
I'm passing data through a FIFO, but when I want to acquire more than X seconds (depends on Sampling Rate) I get the error:
"Error -52000 Occured at Ioen FPGA VI Reference in Host.vi

This error code is undefined. No one has privuded a description for this code, or you might have wied a number that is not an error code to the error code input."

It used to work to sample 30 seconds @ 10 kS/s without any problems. At the moment it doesn't even work to sample 10 seconds. Does this have anything to do with the computer memory?

Thanks,

Tim

[MightyEKA]

Sorry for the bad typing.

"Error -52000 Occured at OPEN* FPGA VI Reference in Host.vi

This error code is undefined. No one has PROVIDED* a description for this code, or you might have WIRED* a number that is not an error code to the error code input."

[Davidek]

Hi Tim

There is a definition for that error, "The specified number of bytes could not be allocated". Very strange that you get that it's undefined. You don't mention what hardware you are using. Is it a cRIO? How have you defined your FIFO?

Best Regards

David

NISW

[MightyEKA]

Hello David!

So what you are saying is that I'm using too much bytes?

I'm using a 9012 controller with a 9229 module. The FIFO's that I'm using is one local FIFO and one Target Host. Both are defined identically: FXP, 2047(?) Elements, 32 bytes, 6 bytes. On the RT-side, the depth is three times the samples.

Regards,

Tim Jansson

[Davidek]

Hi Tim

From what I can tell you are using too much memory on your controller. What, besides the FIFO are you doing in your RT VI? Can you post your project? 

Best Regards

David

Message Edited by Davidek on 12-14-2009 03:55 AM

[MightyEKA]

Hello! 

Yes, of course! I'm building a simple project, but since I'm a beginner I struggle with the project. The project is to acquire data from external devices to the cRIO, with trigger and pre-trigger functions. The trigger works, but I'm still working on the pre trigger and I have no idea how this is going to work. 

I'm using a 9102 chassi! 

Regards,

Tim

[Davidek]

Hi Tim

There are som subVIs missing in the zipfile you posted, FreqCoercion.vi, CalcWithMS2.vi, DMACalsMS.vi and DMACalc.vi.

Best Regards

David

[MightyEKA]

Oh, sorry about that!

Regards,

Tim

[Davidek]

Tim,

I had a look at your code. There are some things that are not really like they should. For example you have a graph on the front panel of the RT host application. That together with the conversion from fixed point to double you do right before that is going to consume memory. You usually don't implement that kind of UI on the RT application, you leave that to a PC Host. Also, you have VIs in the block diagram that are not used. Remove or disable (Disable Diagram structure) code that you don't use. Another thing is that you are issuing the run command before setting the DMA settings. You should set these before Running, but you really don't need to set the depth or start the FIFO. The FIFO starts automatically and the depth on the RT side is per default set to 10 000 elements, which is probably more than you'll need. You also convert the timing to ticks in your own VI. I don't know which version you are suing but in LV 2009 there is a function that does this for you(Sample time to Loop rate.vi).

Looking at the FPGA code I can't understand what you are using the local FIFO to do? You normally use local FIFOs to communicate between two independant loops in the same VI, not transfering data inside the same loop.

Why are you creating an array of a single value, then indexing it in a For loop?

You also have a loop that runs very fast and reads a local variable (Mod1/AI0) updated from a slower loop, causing you to read the same value multiple times.

I don't have the hardware to run it at the moment so I can't recreate the error, but try to remedy the points above and see if the problem remains.

Best Regards

David

Message Edited by Davidek on 12-16-2009 06:32 AM

[MightyEKA]

Hello David!

The local FIFO collects pre trigger samples. At least I hope so. I started building the project from "DMA Reference Triggered Acq  -cRIO" example.

I haven't been using PC Hosts before, but I will try this today.

The SUBvi's that aren't in use are because of laziness. I haven't removed them because I use them from time to time. I will remove everything that isn't in use.

I'm using LV 8.6, but I'm not sure why I have to convert the timing to ticks?

I'll try your changes today and find out if it gets any better.

Perhaps it helps if I explain my project a little bit more.

I need the project to run until it hits a trigger level. I won't know when it should trigger, it could be a matter of seconds, minutes, hours. When this happens, I want it to stop after a selective amount of seconds, lets say 30 seconds. Besides this 30 seconds period, I also want it to show ~a second of pre trigger samples.

Since you do not have access to HW, I will try to explain how it works atm: The trigger function works fine, it triggers and stops after X seconds of samples, then prints this on the graph. It also shows a random amount of pretrigger samples. This because of Local Clear when Local Fifo reaches Time Out. I've tried so many different ways to Clear in a controlled way. But without success.

Thank you for trying 😉

Regards,
Tim  

Message Edited by MightyEKA on 12-17-2009 01:55 AM